Accurate models for estimating area and power of FPGA implementations

Lanping Deng, Kanwaldeep Sobti, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

29 Citations (Scopus)

Abstract

This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficient design space exploration in an automated algorithm-architecture codesign framework. Detailed models for accurately estimating the number of slices, block RAMs and 18×18-bit multipliers for fixed point and floating-point IP cores have been developed. These models are also utilized to develop accurate power models that consider the effect of logic power, signal power, clock power and I/O power. In all cases, the model coefficients have been derived by using curve fitting or regression analysis. The modeling error for the IP cores is very small (average 0.95%). The error for fairly large examples such as floating point implementation of 8-point FFTs is also quite small; it is 1.87% for estimation of number of slices and 3.48% for estimation of power consumption.

Original languageEnglish (US)
Title of host publicationICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Pages1417-1420
Number of pages4
DOIs
StatePublished - 2008
Event2008 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP - Las Vegas, NV, United States
Duration: Mar 31 2008Apr 4 2008

Other

Other2008 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP
CountryUnited States
CityLas Vegas, NV
Period3/31/084/4/08

Fingerprint

Field programmable gate arrays (FPGA)
estimating
floating
space exploration
fast Fourier transformations
curve fitting
multipliers
Curve fitting
Random access storage
Regression analysis
Fast Fourier transforms
clocks
logic
regression analysis
Clocks
Electric power utilization
coefficients
Intellectual property core

Keywords

  • Area and power models
  • FPGA implementation
  • IP core
  • Regression analysis

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Acoustics and Ultrasonics

Cite this

Deng, L., Sobti, K., & Chakrabarti, C. (2008). Accurate models for estimating area and power of FPGA implementations. In ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings (pp. 1417-1420). [4517885] https://doi.org/10.1109/ICASSP.2008.4517885

Accurate models for estimating area and power of FPGA implementations. / Deng, Lanping; Sobti, Kanwaldeep; Chakrabarti, Chaitali.

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. 2008. p. 1417-1420 4517885.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Deng, L, Sobti, K & Chakrabarti, C 2008, Accurate models for estimating area and power of FPGA implementations. in ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings., 4517885, pp. 1417-1420, 2008 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP, Las Vegas, NV, United States, 3/31/08. https://doi.org/10.1109/ICASSP.2008.4517885
Deng L, Sobti K, Chakrabarti C. Accurate models for estimating area and power of FPGA implementations. In ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. 2008. p. 1417-1420. 4517885 https://doi.org/10.1109/ICASSP.2008.4517885
Deng, Lanping ; Sobti, Kanwaldeep ; Chakrabarti, Chaitali. / Accurate models for estimating area and power of FPGA implementations. ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. 2008. pp. 1417-1420
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