Accurate area, time and power models for FPGA-based implementations

Lanping Deng, Kanwaldeep Sobti, Yuanrui Zhang, Chaitali Chakrabarti

Research output: Contribution to journalArticle

23 Scopus citations

Abstract

This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family (Deng et al. 2008). These models are designed to facilitate efficient design space exploration in an automated algorithm-architecture codesign framework. Detailed models for estimating the number of slices, block RAMs and 18×18-bit multipliers for fixed point and floating point IP cores have been developed. These models are also utilized to develop power models that consider the effect of logic power, signal power, clock power and I/O power. Timing models have been developed to predict the latency of the fixed point and floating point IP cores. In all cases, the model coefficients have been derived by using curve fitting or regression analysis. The modeling error is quite small for single IP cores; the error for the area estimate, for instance, is on the average 0.95%. The error for fairly large examples such as floating point implementation of 8-point FFTs is also quite small; it is 1.87% for estimation of number of slices and 3.48% for estimation of power consumption. The proposed models have also been integrated into a hardware-software partitioning tool to facilitate design space exploration under area and time constraints.

Original languageEnglish (US)
Pages (from-to)39-50
Number of pages12
JournalJournal of Signal Processing Systems
Volume63
Issue number1
DOIs
StatePublished - Apr 1 2011

    Fingerprint

Keywords

  • Design space exploration
  • Estimators for area
  • FPGA
  • IP core
  • Power
  • Regression analysis
  • Time

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Theoretical Computer Science
  • Signal Processing
  • Information Systems
  • Modeling and Simulation
  • Hardware and Architecture

Cite this