21 Citations (Scopus)

Abstract

This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family (Deng et al. 2008). These models are designed to facilitate efficient design space exploration in an automated algorithm-architecture codesign framework. Detailed models for estimating the number of slices, block RAMs and 18×18-bit multipliers for fixed point and floating point IP cores have been developed. These models are also utilized to develop power models that consider the effect of logic power, signal power, clock power and I/O power. Timing models have been developed to predict the latency of the fixed point and floating point IP cores. In all cases, the model coefficients have been derived by using curve fitting or regression analysis. The modeling error is quite small for single IP cores; the error for the area estimate, for instance, is on the average 0.95%. The error for fairly large examples such as floating point implementation of 8-point FFTs is also quite small; it is 1.87% for estimation of number of slices and 3.48% for estimation of power consumption. The proposed models have also been integrated into a hardware-software partitioning tool to facilitate design space exploration under area and time constraints.

Original languageEnglish (US)
Pages (from-to)39-50
Number of pages12
JournalJournal of Signal Processing Systems
Volume63
Issue number1
DOIs
StatePublished - Apr 2011

Fingerprint

Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Floating point
Design Space Exploration
Slice
Model
Hardware/software Partitioning
Fixed point
Co-design
FPGA Implementation
Modeling Error
Curve fitting
Random access storage
Regression Analysis
Regression analysis
Fast Fourier transforms
Power Consumption
Multiplier
Latency
Clocks

Keywords

  • Design space exploration
  • Estimators for area
  • FPGA
  • IP core
  • Power
  • Regression analysis
  • Time

ASJC Scopus subject areas

  • Hardware and Architecture
  • Information Systems
  • Signal Processing
  • Theoretical Computer Science
  • Control and Systems Engineering
  • Modeling and Simulation

Cite this

Accurate area, time and power models for FPGA-based implementations. / Deng, Lanping; Sobti, Kanwaldeep; Zhang, Yuanrui; Chakrabarti, Chaitali.

In: Journal of Signal Processing Systems, Vol. 63, No. 1, 04.2011, p. 39-50.

Research output: Contribution to journalArticle

Deng, Lanping ; Sobti, Kanwaldeep ; Zhang, Yuanrui ; Chakrabarti, Chaitali. / Accurate area, time and power models for FPGA-based implementations. In: Journal of Signal Processing Systems. 2011 ; Vol. 63, No. 1. pp. 39-50.
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