A wide locking-range, low phase-noise and high output power D-Band SiGe PLL

Saeed Zeinolabedinzadeh, Ickhung Song, Mehmet Kaynak, John D. Cressler

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A fully integrated, wide locking-range fundamental frequency SiGe phase-locked-loop (PLL) at D-band is proposed which utilizes coupled voltage-controlled-oscillators (VCOs) to generate and distribute balanced RF signals in a symmetric and compact form factor. The proposed technique facilitates the balanced LO distribution, increases the output power, improves the phase noise, and increases the locking range of frequency dividers at the same time, all at the cost of increased DC power consumption. The designed VCO achieves better than 10% DC-to-RF conversion efficiency across the entire tuning-range and provides output power of better than +8 dBm. The VCO achieves a FoMt of more than 194, which, to the best of our knowledge is the highest FoMt among the reported D-band VCOs. The PLL was fully integrated in a 130 nm SiGe BiCMOS technology. This PLL locks at 105-117 GHz. It achieves a phase noise of better than -100 dBc/ Hz and -121 dBc/ Hz at 1 MHz and 10 MHz offset from a 116 GHz carrier, respectively. The measured average output power is better than +8 dBm across the entire locking-range.

Original languageEnglish (US)
Title of host publication2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages35-38
Number of pages4
ISBN (Electronic)9781728121291
DOIs
StatePublished - Jan 2020
Event20th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2020 - San Antonio, United States
Duration: Jan 26 2020Jan 29 2020

Publication series

Name2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2020

Conference

Conference20th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2020
CountryUnited States
CitySan Antonio
Period1/26/201/29/20

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Signal Processing
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Zeinolabedinzadeh, S., Song, I., Kaynak, M., & Cressler, J. D. (2020). A wide locking-range, low phase-noise and high output power D-Band SiGe PLL. In 2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2020 (pp. 35-38). [9040189] (2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SIRF46766.2020.9040189