A wafer-level defect screening technique to reduce test and packaging costs for "big-D/small-A" mixed-signal SoCs

Sudarshan Bahukudumbi, Sulc Ozev, Krishnendu Chakrabarty, Vikram Iyengar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of "big-D/small-A" mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is developed to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss and packaging costs. Experimental results are presented for a typical mixed-signal "big-D/small-A" SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.

Original languageEnglish (US)
Title of host publicationProceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Pages823-828
Number of pages6
DOIs
StatePublished - Dec 1 2007
Externally publishedYes
EventASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan
Duration: Jan 23 2007Jan 27 2007

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

OtherASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
CountryJapan
CityYokohama
Period1/23/071/27/07

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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    Bahukudumbi, S., Ozev, S., Chakrabarty, K., & Iyengar, V. (2007). A wafer-level defect screening technique to reduce test and packaging costs for "big-D/small-A" mixed-signal SoCs. In Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 (pp. 823-828). [4196137] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2007.358091