Abstract

In this paper, a supply chain simulation testbed for the semiconductor industry is proposed. We start by identifying requirements for such reference datasets, and then we identify the main building blocks. The nodes of the supply chain that represent semiconductor wafer fabrication facilities (wafer fabs) are built on a simulation model from the measurement and improvement of manufacturing capacity project. We present two techniques to reduce the modeling and computational burden that are able to deal with load-dependent cycle times in single front-end and back-end facilities and in the overall network. The first method models in detail only the bottlenecks in the nodes of the supply chain, while the second one uses empirical distributions for cycle time and throughput. The quality of these reduction techniques is assessed by comparing the detailed model and the models with a reduced level of detail. We present an application scenario for the testbed by simulating a semiconductor supply network. In addition, the usage of the testbed is discussed.

Original languageEnglish (US)
Article number7944690
Pages (from-to)293-305
Number of pages13
JournalIEEE Transactions on Semiconductor Manufacturing
Volume30
Issue number3
DOIs
StatePublished - Aug 1 2017

Fingerprint

Testbeds
Supply chains
Semiconductor materials
cycles
manufacturing
simulation
industries
Throughput
wafers
Fabrication
requirements
fabrication
Industry

Keywords

  • semiconductor manufacturing
  • Simulation
  • simulation experiments
  • supply chain management
  • testbed

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

Cite this

A testbed for simulating semiconductor supply chains. / Ewen, Hanna; Monch, Lars; Ehm, Hans; Ponsignon, Thomas; Fowler, John; Forstner, Lisa.

In: IEEE Transactions on Semiconductor Manufacturing, Vol. 30, No. 3, 7944690, 01.08.2017, p. 293-305.

Research output: Contribution to journalArticle

Ewen, H, Monch, L, Ehm, H, Ponsignon, T, Fowler, J & Forstner, L 2017, 'A testbed for simulating semiconductor supply chains', IEEE Transactions on Semiconductor Manufacturing, vol. 30, no. 3, 7944690, pp. 293-305. https://doi.org/10.1109/TSM.2017.2713775
Ewen, Hanna ; Monch, Lars ; Ehm, Hans ; Ponsignon, Thomas ; Fowler, John ; Forstner, Lisa. / A testbed for simulating semiconductor supply chains. In: IEEE Transactions on Semiconductor Manufacturing. 2017 ; Vol. 30, No. 3. pp. 293-305.
@article{a067e3c5fec14f03875261e15d9c293b,
title = "A testbed for simulating semiconductor supply chains",
abstract = "In this paper, a supply chain simulation testbed for the semiconductor industry is proposed. We start by identifying requirements for such reference datasets, and then we identify the main building blocks. The nodes of the supply chain that represent semiconductor wafer fabrication facilities (wafer fabs) are built on a simulation model from the measurement and improvement of manufacturing capacity project. We present two techniques to reduce the modeling and computational burden that are able to deal with load-dependent cycle times in single front-end and back-end facilities and in the overall network. The first method models in detail only the bottlenecks in the nodes of the supply chain, while the second one uses empirical distributions for cycle time and throughput. The quality of these reduction techniques is assessed by comparing the detailed model and the models with a reduced level of detail. We present an application scenario for the testbed by simulating a semiconductor supply network. In addition, the usage of the testbed is discussed.",
keywords = "semiconductor manufacturing, Simulation, simulation experiments, supply chain management, testbed",
author = "Hanna Ewen and Lars Monch and Hans Ehm and Thomas Ponsignon and John Fowler and Lisa Forstner",
year = "2017",
month = "8",
day = "1",
doi = "10.1109/TSM.2017.2713775",
language = "English (US)",
volume = "30",
pages = "293--305",
journal = "IEEE Transactions on Semiconductor Manufacturing",
issn = "0894-6507",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

TY - JOUR

T1 - A testbed for simulating semiconductor supply chains

AU - Ewen, Hanna

AU - Monch, Lars

AU - Ehm, Hans

AU - Ponsignon, Thomas

AU - Fowler, John

AU - Forstner, Lisa

PY - 2017/8/1

Y1 - 2017/8/1

N2 - In this paper, a supply chain simulation testbed for the semiconductor industry is proposed. We start by identifying requirements for such reference datasets, and then we identify the main building blocks. The nodes of the supply chain that represent semiconductor wafer fabrication facilities (wafer fabs) are built on a simulation model from the measurement and improvement of manufacturing capacity project. We present two techniques to reduce the modeling and computational burden that are able to deal with load-dependent cycle times in single front-end and back-end facilities and in the overall network. The first method models in detail only the bottlenecks in the nodes of the supply chain, while the second one uses empirical distributions for cycle time and throughput. The quality of these reduction techniques is assessed by comparing the detailed model and the models with a reduced level of detail. We present an application scenario for the testbed by simulating a semiconductor supply network. In addition, the usage of the testbed is discussed.

AB - In this paper, a supply chain simulation testbed for the semiconductor industry is proposed. We start by identifying requirements for such reference datasets, and then we identify the main building blocks. The nodes of the supply chain that represent semiconductor wafer fabrication facilities (wafer fabs) are built on a simulation model from the measurement and improvement of manufacturing capacity project. We present two techniques to reduce the modeling and computational burden that are able to deal with load-dependent cycle times in single front-end and back-end facilities and in the overall network. The first method models in detail only the bottlenecks in the nodes of the supply chain, while the second one uses empirical distributions for cycle time and throughput. The quality of these reduction techniques is assessed by comparing the detailed model and the models with a reduced level of detail. We present an application scenario for the testbed by simulating a semiconductor supply network. In addition, the usage of the testbed is discussed.

KW - semiconductor manufacturing

KW - Simulation

KW - simulation experiments

KW - supply chain management

KW - testbed

UR - http://www.scopus.com/inward/record.url?scp=85029425782&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85029425782&partnerID=8YFLogxK

U2 - 10.1109/TSM.2017.2713775

DO - 10.1109/TSM.2017.2713775

M3 - Article

AN - SCOPUS:85029425782

VL - 30

SP - 293

EP - 305

JO - IEEE Transactions on Semiconductor Manufacturing

JF - IEEE Transactions on Semiconductor Manufacturing

SN - 0894-6507

IS - 3

M1 - 7944690

ER -