A technique for throughput and register optimization during resource constrained pipelined scheduling

Nagendran Rangan, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a novel method for resource constrained and register aware pipelined scheduling of data flow graphs. In a VLSI circuit, it is essential to minimize area, and to obtain a schedule that requires as few registers as possible. A technique that combines path-based scheduling algorithm and retiming heuristic has been developed to produce a schedule with maximum throughput while minimizing the register requirement. The effectiveness of the proposed technique is demonstrated by experimentation with several representative high level synthesis benchmarks and loop kernels. It is observed that our technique produces an average of 22.76% reduction in register requirements in comparison with rotation scheduling [1] when a bottom-up scheduling method is used. For the topdown scheduling case the technique produces an average reduction of 20.22% in register requirements.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
Pages564-569
Number of pages6
StatePublished - 2005
Event18th International Conference on VLSI Design: Power Aware Design of VLSI Systems - Kolkata, India
Duration: Jan 3 2005Jan 7 2005

Other

Other18th International Conference on VLSI Design: Power Aware Design of VLSI Systems
CountryIndia
CityKolkata
Period1/3/051/7/05

Fingerprint

Scheduling
Throughput
Data flow graphs
VLSI circuits
Scheduling algorithms

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Rangan, N., & Chatha, K. S. (2005). A technique for throughput and register optimization during resource constrained pipelined scheduling. In Proceedings of the IEEE International Conference on VLSI Design (pp. 564-569)

A technique for throughput and register optimization during resource constrained pipelined scheduling. / Rangan, Nagendran; Chatha, Karam S.

Proceedings of the IEEE International Conference on VLSI Design. 2005. p. 564-569.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rangan, N & Chatha, KS 2005, A technique for throughput and register optimization during resource constrained pipelined scheduling. in Proceedings of the IEEE International Conference on VLSI Design. pp. 564-569, 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems, Kolkata, India, 1/3/05.
Rangan N, Chatha KS. A technique for throughput and register optimization during resource constrained pipelined scheduling. In Proceedings of the IEEE International Conference on VLSI Design. 2005. p. 564-569
Rangan, Nagendran ; Chatha, Karam S. / A technique for throughput and register optimization during resource constrained pipelined scheduling. Proceedings of the IEEE International Conference on VLSI Design. 2005. pp. 564-569
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