A technique for low energy mapping and routing in network-on-chip architectures

Krishnan Srinivasan, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

103 Citations (Scopus)

Abstract

Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh based topologies requires mapping of cores to router ports, and routing of traffic traces such that the bandwidth and latency constraints are satisfied. We present a novel automated design technique that solves the mesh based NoC design problem with an objective of minimizing the communication energy. In contrast to existing research that only take bandwidth constraints as inputs, our technique solves the NoC design problem in the presence of bandwidth as well as latency constraints. We compare our technique with a recent work called NMAP and an optimal MILP based formulation. We prove that the complexity of our technique is lower than that of NMAP. For the latency constrained case, while NMAP fails on most test cases, our technique is able to generate high quality results. In comparison to the MILP formulation, the results produced by our technique are within 14% of the optimal.

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design
Pages387-392
Number of pages6
StatePublished - 2005
Event2005 International Symposium on Low Power Electronics and Design - San Diego, CA, United States
Duration: Aug 8 2005Aug 10 2005

Other

Other2005 International Symposium on Low Power Electronics and Design
CountryUnited States
CitySan Diego, CA
Period8/8/058/10/05

Fingerprint

Bandwidth
Communication
Routers
Telecommunication traffic
Topology
Network-on-chip
System-on-chip

Keywords

  • Automated design
  • Core mapping
  • Mesh topology
  • Network-on-Chip
  • Routing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Srinivasan, K., & Chatha, K. S. (2005). A technique for low energy mapping and routing in network-on-chip architectures. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 387-392)

A technique for low energy mapping and routing in network-on-chip architectures. / Srinivasan, Krishnan; Chatha, Karam S.

Proceedings of the International Symposium on Low Power Electronics and Design. 2005. p. 387-392.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Srinivasan, K & Chatha, KS 2005, A technique for low energy mapping and routing in network-on-chip architectures. in Proceedings of the International Symposium on Low Power Electronics and Design. pp. 387-392, 2005 International Symposium on Low Power Electronics and Design, San Diego, CA, United States, 8/8/05.
Srinivasan K, Chatha KS. A technique for low energy mapping and routing in network-on-chip architectures. In Proceedings of the International Symposium on Low Power Electronics and Design. 2005. p. 387-392
Srinivasan, Krishnan ; Chatha, Karam S. / A technique for low energy mapping and routing in network-on-chip architectures. Proceedings of the International Symposium on Low Power Electronics and Design. 2005. pp. 387-392
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