A technique for estimating signal activity in logic circuits

Hong Yu Xie, Sarma Vrudhula

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

In this paper an efficient technique for estimating the average number of signal transitions in CMOS logic circuits is presented. A logic signal is modeled as a two state, discrete-time Markov chain, that is characterized by two parameters. The steady-state average number of transitions on a signal is expressed as a function of the Markov chain parameters. Formulas for the two parameters associated with the gate output as a function of the corresponding parameters associated with the gate input are derived. This allows estimation of signal transitions at all gates by local propagation of the parameters. For circuits without reconvergent, the local propagation provides very accurate estimates and the time to obtain the estimates is a negligible fraction of the time required to perform logic simulation. For circuits with reconvergent fanout, the estimation procedure is based on the (local) use of OBBDs. This scheme has the flexibility of trading off between speed and accuracy by allowing the user to specify the number of levels of reconvergent fanout that are to considered. Results of experiments carried out on a large number of benchmark circuits are given. The theoretical estimates of switching activity are compared with those obtained via simulation. The experiments also examine the number of levels of logic that need to be examined in the presence of reconvergent fanout.

Original languageEnglish (US)
Pages (from-to)141-151
Number of pages11
JournalIntegrated Computer-Aided Engineering
Volume5
Issue number2
StatePublished - 1998

Fingerprint

Logic circuits
Logic
Markov processes
Networks (circuits)
Two Parameters
Markov chain
Estimate
Propagation
Experiments
Experiment
Simulation
Discrete-time
Flexibility
Benchmark
Output

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computational Theory and Mathematics
  • Computer Science Applications
  • Engineering (miscellaneous)

Cite this

A technique for estimating signal activity in logic circuits. / Xie, Hong Yu; Vrudhula, Sarma.

In: Integrated Computer-Aided Engineering, Vol. 5, No. 2, 1998, p. 141-151.

Research output: Contribution to journalArticle

@article{429007cf33074c82b780bf7f97262f68,
title = "A technique for estimating signal activity in logic circuits",
abstract = "In this paper an efficient technique for estimating the average number of signal transitions in CMOS logic circuits is presented. A logic signal is modeled as a two state, discrete-time Markov chain, that is characterized by two parameters. The steady-state average number of transitions on a signal is expressed as a function of the Markov chain parameters. Formulas for the two parameters associated with the gate output as a function of the corresponding parameters associated with the gate input are derived. This allows estimation of signal transitions at all gates by local propagation of the parameters. For circuits without reconvergent, the local propagation provides very accurate estimates and the time to obtain the estimates is a negligible fraction of the time required to perform logic simulation. For circuits with reconvergent fanout, the estimation procedure is based on the (local) use of OBBDs. This scheme has the flexibility of trading off between speed and accuracy by allowing the user to specify the number of levels of reconvergent fanout that are to considered. Results of experiments carried out on a large number of benchmark circuits are given. The theoretical estimates of switching activity are compared with those obtained via simulation. The experiments also examine the number of levels of logic that need to be examined in the presence of reconvergent fanout.",
author = "Xie, {Hong Yu} and Sarma Vrudhula",
year = "1998",
language = "English (US)",
volume = "5",
pages = "141--151",
journal = "Integrated Computer-Aided Engineering",
issn = "1069-2509",
publisher = "IOS Press",
number = "2",

}

TY - JOUR

T1 - A technique for estimating signal activity in logic circuits

AU - Xie, Hong Yu

AU - Vrudhula, Sarma

PY - 1998

Y1 - 1998

N2 - In this paper an efficient technique for estimating the average number of signal transitions in CMOS logic circuits is presented. A logic signal is modeled as a two state, discrete-time Markov chain, that is characterized by two parameters. The steady-state average number of transitions on a signal is expressed as a function of the Markov chain parameters. Formulas for the two parameters associated with the gate output as a function of the corresponding parameters associated with the gate input are derived. This allows estimation of signal transitions at all gates by local propagation of the parameters. For circuits without reconvergent, the local propagation provides very accurate estimates and the time to obtain the estimates is a negligible fraction of the time required to perform logic simulation. For circuits with reconvergent fanout, the estimation procedure is based on the (local) use of OBBDs. This scheme has the flexibility of trading off between speed and accuracy by allowing the user to specify the number of levels of reconvergent fanout that are to considered. Results of experiments carried out on a large number of benchmark circuits are given. The theoretical estimates of switching activity are compared with those obtained via simulation. The experiments also examine the number of levels of logic that need to be examined in the presence of reconvergent fanout.

AB - In this paper an efficient technique for estimating the average number of signal transitions in CMOS logic circuits is presented. A logic signal is modeled as a two state, discrete-time Markov chain, that is characterized by two parameters. The steady-state average number of transitions on a signal is expressed as a function of the Markov chain parameters. Formulas for the two parameters associated with the gate output as a function of the corresponding parameters associated with the gate input are derived. This allows estimation of signal transitions at all gates by local propagation of the parameters. For circuits without reconvergent, the local propagation provides very accurate estimates and the time to obtain the estimates is a negligible fraction of the time required to perform logic simulation. For circuits with reconvergent fanout, the estimation procedure is based on the (local) use of OBBDs. This scheme has the flexibility of trading off between speed and accuracy by allowing the user to specify the number of levels of reconvergent fanout that are to considered. Results of experiments carried out on a large number of benchmark circuits are given. The theoretical estimates of switching activity are compared with those obtained via simulation. The experiments also examine the number of levels of logic that need to be examined in the presence of reconvergent fanout.

UR - http://www.scopus.com/inward/record.url?scp=0031682839&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031682839&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0031682839

VL - 5

SP - 141

EP - 151

JO - Integrated Computer-Aided Engineering

JF - Integrated Computer-Aided Engineering

SN - 1069-2509

IS - 2

ER -