### Abstract

In this paper an efficient technique for estimating the average number of signal transitions in CMOS logic circuits is presented. A logic signal is modeled as a two state, discrete-time Markov chain, that is characterized by two parameters. The steady-state average number of transitions on a signal is expressed as a function of the Markov chain parameters. Formulas for the two parameters associated with the gate output as a function of the corresponding parameters associated with the gate input are derived. This allows estimation of signal transitions at all gates by local propagation of the parameters. For circuits without reconvergent, the local propagation provides very accurate estimates and the time to obtain the estimates is a negligible fraction of the time required to perform logic simulation. For circuits with reconvergent fanout, the estimation procedure is based on the (local) use of OBBDs. This scheme has the flexibility of trading off between speed and accuracy by allowing the user to specify the number of levels of reconvergent fanout that are to considered. Results of experiments carried out on a large number of benchmark circuits are given. The theoretical estimates of switching activity are compared with those obtained via simulation. The experiments also examine the number of levels of logic that need to be examined in the presence of reconvergent fanout.

Original language | English (US) |
---|---|

Pages (from-to) | 141-151 |

Number of pages | 11 |

Journal | Integrated Computer-Aided Engineering |

Volume | 5 |

Issue number | 2 |

State | Published - 1998 |

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### ASJC Scopus subject areas

- Artificial Intelligence
- Computational Theory and Mathematics
- Computer Science Applications
- Engineering (miscellaneous)

### Cite this

*Integrated Computer-Aided Engineering*,

*5*(2), 141-151.

**A technique for estimating signal activity in logic circuits.** / Xie, Hong Yu; Vrudhula, Sarma.

Research output: Contribution to journal › Article

*Integrated Computer-Aided Engineering*, vol. 5, no. 2, pp. 141-151.

}

TY - JOUR

T1 - A technique for estimating signal activity in logic circuits

AU - Xie, Hong Yu

AU - Vrudhula, Sarma

PY - 1998

Y1 - 1998

N2 - In this paper an efficient technique for estimating the average number of signal transitions in CMOS logic circuits is presented. A logic signal is modeled as a two state, discrete-time Markov chain, that is characterized by two parameters. The steady-state average number of transitions on a signal is expressed as a function of the Markov chain parameters. Formulas for the two parameters associated with the gate output as a function of the corresponding parameters associated with the gate input are derived. This allows estimation of signal transitions at all gates by local propagation of the parameters. For circuits without reconvergent, the local propagation provides very accurate estimates and the time to obtain the estimates is a negligible fraction of the time required to perform logic simulation. For circuits with reconvergent fanout, the estimation procedure is based on the (local) use of OBBDs. This scheme has the flexibility of trading off between speed and accuracy by allowing the user to specify the number of levels of reconvergent fanout that are to considered. Results of experiments carried out on a large number of benchmark circuits are given. The theoretical estimates of switching activity are compared with those obtained via simulation. The experiments also examine the number of levels of logic that need to be examined in the presence of reconvergent fanout.

AB - In this paper an efficient technique for estimating the average number of signal transitions in CMOS logic circuits is presented. A logic signal is modeled as a two state, discrete-time Markov chain, that is characterized by two parameters. The steady-state average number of transitions on a signal is expressed as a function of the Markov chain parameters. Formulas for the two parameters associated with the gate output as a function of the corresponding parameters associated with the gate input are derived. This allows estimation of signal transitions at all gates by local propagation of the parameters. For circuits without reconvergent, the local propagation provides very accurate estimates and the time to obtain the estimates is a negligible fraction of the time required to perform logic simulation. For circuits with reconvergent fanout, the estimation procedure is based on the (local) use of OBBDs. This scheme has the flexibility of trading off between speed and accuracy by allowing the user to specify the number of levels of reconvergent fanout that are to considered. Results of experiments carried out on a large number of benchmark circuits are given. The theoretical estimates of switching activity are compared with those obtained via simulation. The experiments also examine the number of levels of logic that need to be examined in the presence of reconvergent fanout.

UR - http://www.scopus.com/inward/record.url?scp=0031682839&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031682839&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0031682839

VL - 5

SP - 141

EP - 151

JO - Integrated Computer-Aided Engineering

JF - Integrated Computer-Aided Engineering

SN - 1069-2509

IS - 2

ER -