A system-level solution to domino synthesis with 2 GHz application

B. Chappell, X. Wang, P. Patra, P. Saxena, J. Vendrell, Sandeep Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

System structure and a taped out 0.18u 2GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Pages164-171
Number of pages8
StatePublished - 2002
EventInternational Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors - Freiburg, Germany
Duration: Sep 16 2002Sep 18 2002

Other

OtherInternational Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors
CountryGermany
CityFreiburg
Period9/16/029/18/02

Fingerprint

Silicon
Costs

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Chappell, B., Wang, X., Patra, P., Saxena, P., Vendrell, J., Gupta, S., ... Jain, S. (2002). A system-level solution to domino synthesis with 2 GHz application. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 164-171)

A system-level solution to domino synthesis with 2 GHz application. / Chappell, B.; Wang, X.; Patra, P.; Saxena, P.; Vendrell, J.; Gupta, Sandeep; Varadarajan, S.; Gomes, W.; Hussain, S.; Krishnamurthy, H.; Venkateshmurthy, M.; Jain, S.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. 2002. p. 164-171.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chappell, B, Wang, X, Patra, P, Saxena, P, Vendrell, J, Gupta, S, Varadarajan, S, Gomes, W, Hussain, S, Krishnamurthy, H, Venkateshmurthy, M & Jain, S 2002, A system-level solution to domino synthesis with 2 GHz application. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. pp. 164-171, International Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors, Freiburg, Germany, 9/16/02.
Chappell B, Wang X, Patra P, Saxena P, Vendrell J, Gupta S et al. A system-level solution to domino synthesis with 2 GHz application. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. 2002. p. 164-171
Chappell, B. ; Wang, X. ; Patra, P. ; Saxena, P. ; Vendrell, J. ; Gupta, Sandeep ; Varadarajan, S. ; Gomes, W. ; Hussain, S. ; Krishnamurthy, H. ; Venkateshmurthy, M. ; Jain, S. / A system-level solution to domino synthesis with 2 GHz application. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. 2002. pp. 164-171
@inproceedings{2191e281e13b4170b4deeb13e1fc4e6d,
title = "A system-level solution to domino synthesis with 2 GHz application",
abstract = "System structure and a taped out 0.18u 2GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.",
author = "B. Chappell and X. Wang and P. Patra and P. Saxena and J. Vendrell and Sandeep Gupta and S. Varadarajan and W. Gomes and S. Hussain and H. Krishnamurthy and M. Venkateshmurthy and S. Jain",
year = "2002",
language = "English (US)",
pages = "164--171",
booktitle = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",

}

TY - GEN

T1 - A system-level solution to domino synthesis with 2 GHz application

AU - Chappell, B.

AU - Wang, X.

AU - Patra, P.

AU - Saxena, P.

AU - Vendrell, J.

AU - Gupta, Sandeep

AU - Varadarajan, S.

AU - Gomes, W.

AU - Hussain, S.

AU - Krishnamurthy, H.

AU - Venkateshmurthy, M.

AU - Jain, S.

PY - 2002

Y1 - 2002

N2 - System structure and a taped out 0.18u 2GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.

AB - System structure and a taped out 0.18u 2GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.

UR - http://www.scopus.com/inward/record.url?scp=0036397195&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036397195&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0036397195

SP - 164

EP - 171

BT - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

ER -