A system-level solution to domino synthesis with 2 GHz application

B. Chappell, X. Wang, P. Patra, P. Saxena, J. Vendrell, Sandeep Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

System structure and a taped out 0.18u 2GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Pages164-171
Number of pages8
StatePublished - 2002
EventInternational Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors - Freiburg, Germany
Duration: Sep 16 2002Sep 18 2002

Other

OtherInternational Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors
CountryGermany
CityFreiburg
Period9/16/029/18/02

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A system-level solution to domino synthesis with 2 GHz application'. Together they form a unique fingerprint.

Cite this