Abstract
System structure and a taped out 0.18u 2GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |
Pages | 164-171 |
Number of pages | 8 |
State | Published - 2002 |
Event | International Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors - Freiburg, Germany Duration: Sep 16 2002 → Sep 18 2002 |
Other
Other | International Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors |
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Country/Territory | Germany |
City | Freiburg |
Period | 9/16/02 → 9/18/02 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering