A survey on hardware security techniques targeting low-power SoC designs

Alan Ehret, Karen Gettings, Bruce R. Jordan, Michel A. Kinsy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

In this work, we survey hardware-based security techniques applicable to low-power system-on-chip designs. Techniques related to a system's processing elements, volatile main memory and caches, non-volatile memory and on-chip interconnects are examined. Threat models for each subsystem and technique are considered. Performance overheads and other trade-offs for each technique are discussed. Defenses with similar threat models are compared.

Original languageEnglish (US)
Title of host publication2019 IEEE High Performance Extreme Computing Conference, HPEC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728150208
DOIs
StatePublished - Sep 2019
Externally publishedYes
Event2019 IEEE High Performance Extreme Computing Conference, HPEC 2019 - Waltham, United States
Duration: Sep 24 2019Sep 26 2019

Publication series

Name2019 IEEE High Performance Extreme Computing Conference, HPEC 2019

Conference

Conference2019 IEEE High Performance Extreme Computing Conference, HPEC 2019
Country/TerritoryUnited States
CityWaltham
Period9/24/199/26/19

Keywords

  • Hardware Security
  • Network-on-chip
  • Oblivious RAM
  • PUF
  • Secure Enclave
  • System-on-Chip

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Networks and Communications
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality
  • Artificial Intelligence

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