TY - GEN
T1 - A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron
AU - Azari, Elham
AU - Wagle, Ankit
AU - Khatri, Sunil
AU - Vrudhula, Sarma
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/3
Y1 - 2020/3
N2 - In this paper, we present an efficient statistical approach for analyzing the robustness of threshold logic gates in the presence of process variations and using the results of that analysis to tune the weights of the threshold gate to maximize yield. Although the proposed methodology is completely general and can be applied to any circuit (digital, mixed-signal or analog), we demonstrate it using the flash transistor based threshold logic gate reported in [1]. The statistical approach presented in this paper involves construction of an efficient database and the design of a stochastic simulator based on an extension to the polynomial chaos technique. The results demonstrate that this methodology when using the stochastic simulator achieves a maximum speed up of 56.5X in reducing the number of HSPICE iterations without loss of accuracy.
AB - In this paper, we present an efficient statistical approach for analyzing the robustness of threshold logic gates in the presence of process variations and using the results of that analysis to tune the weights of the threshold gate to maximize yield. Although the proposed methodology is completely general and can be applied to any circuit (digital, mixed-signal or analog), we demonstrate it using the flash transistor based threshold logic gate reported in [1]. The statistical approach presented in this paper involves construction of an efficient database and the design of a stochastic simulator based on an extension to the polynomial chaos technique. The results demonstrate that this methodology when using the stochastic simulator achieves a maximum speed up of 56.5X in reducing the number of HSPICE iterations without loss of accuracy.
KW - arbitrary polynomial chaos
KW - binary perceptron
KW - process variation
KW - stochastic simulator
UR - http://www.scopus.com/inward/record.url?scp=85089940126&partnerID=8YFLogxK
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U2 - 10.1109/ISQED48828.2020.9136979
DO - 10.1109/ISQED48828.2020.9136979
M3 - Conference contribution
AN - SCOPUS:85089940126
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 141
EP - 148
BT - Proceedings of the 21st International Symposium on Quality Electronic Design, ISQED 2020
PB - IEEE Computer Society
T2 - 21st International Symposium on Quality Electronic Design, ISQED 2020
Y2 - 25 March 2020 through 26 March 2020
ER -