Abstract
An internet protocol (IP) router forwards packets based on their destination address by finding the longest matching prefix in internal lookup tables. In this paper, a fully static CAM that directly determines the next hop among the stored addresses is described. The proposed design achieves high lookup throughput, optimal memory utilization, integrated priority encoding, and high power efficiency. The proposed address look up architecture is 81.2% more energy efficient than a TCAM implementation while achieving 1.6× higher operating frequency. The proposed CAM uses 67.2% less energy than a previous dynamic internet protocol CAM (IPCAM) design. Simulations carried out using a bulk CMOS 65-nm foundry process show the proposed IPCAM circuits can operate above 1 GHz. With dynamic voltage scaling to VDD = 0.6 V, the proposed design uses 0.85 fJ/bit/search at speeds adequate for 10 G Ethernet requirements. The all static design is amenable to automated circuit design flows, as demonstrated by porting to a commercial 45-nm cell library implementation, and can be pipelined. Finally, the proposed circuit architecture is shown to be scalable to IPv6.
Original language | English (US) |
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Pages (from-to) | 350-363 |
Number of pages | 14 |
Journal | Journal of Low Power Electronics |
Volume | 7 |
Issue number | 3 |
DOIs | |
State | Published - 2011 |
Keywords
- Associative Memories
- CIDR
- Content Addressable Memory (CAM)
- IPv4
- IPv6
- Internet Protocol (IP) Routing
- LongestPrefix atch
- Priority Encoder
- Router
- Scalability
- Ternary CAM (TCAM)
ASJC Scopus subject areas
- Electrical and Electronic Engineering