A Soft-Error Mitigated Microprocessor With Software Controlled Error Reporting and Recovery

Chad Farnsworth, Lawrence T. Clark, Anudeep R. Gogulamudi, Vinay Vashishtha, Aditya Gujja

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A MIPS 4Kc compliant embedded microprocessor design that incorporates architectural features for software controlled soft-error recovery is presented. The design leverages classical fault tolerance techniques, e.g., error detection and instruction restart, implemented at the micro-architectural level, and added instructions for error recovery. Soft-errors are detected as the instructions commit to architectural state. At this point, an exception is taken and software recovers the correct machine state and restarts execution. The software recovery allows full machine inspection to determine error root causes. Added instructions also facilitate silicon validation of the hardware and software recovery mechanisms. The design is implemented in a commercial low standby power 90-nm bulk CMOS process and the prototype operates at up to 336 MHz. Finally, proton broad beam irradiation results are presented. The processor demonstrates correct recovery, resuming program operation, from over 500 detected soft-errors, with no unrecoverable errors.

Original languageEnglish (US)
JournalIEEE Transactions on Nuclear Science
DOIs
StateAccepted/In press - Jul 18 2016

Fingerprint

microprocessors
Microprocessor chips
recovery
computer programs
Recovery
education
Error detection
Fault tolerance
Protons
Inspection
fault tolerance
Irradiation
Hardware
Silicon
central processing units
inspection
CMOS
hardware
prototypes
irradiation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Nuclear Energy and Engineering
  • Nuclear and High Energy Physics

Cite this

A Soft-Error Mitigated Microprocessor With Software Controlled Error Reporting and Recovery. / Farnsworth, Chad; Clark, Lawrence T.; Gogulamudi, Anudeep R.; Vashishtha, Vinay; Gujja, Aditya.

In: IEEE Transactions on Nuclear Science, 18.07.2016.

Research output: Contribution to journalArticle

Farnsworth, Chad ; Clark, Lawrence T. ; Gogulamudi, Anudeep R. ; Vashishtha, Vinay ; Gujja, Aditya. / A Soft-Error Mitigated Microprocessor With Software Controlled Error Reporting and Recovery. In: IEEE Transactions on Nuclear Science. 2016.
@article{21ff8d302bea4db392592cf2fbaa8a4a,
title = "A Soft-Error Mitigated Microprocessor With Software Controlled Error Reporting and Recovery",
abstract = "A MIPS 4Kc compliant embedded microprocessor design that incorporates architectural features for software controlled soft-error recovery is presented. The design leverages classical fault tolerance techniques, e.g., error detection and instruction restart, implemented at the micro-architectural level, and added instructions for error recovery. Soft-errors are detected as the instructions commit to architectural state. At this point, an exception is taken and software recovers the correct machine state and restarts execution. The software recovery allows full machine inspection to determine error root causes. Added instructions also facilitate silicon validation of the hardware and software recovery mechanisms. The design is implemented in a commercial low standby power 90-nm bulk CMOS process and the prototype operates at up to 336 MHz. Finally, proton broad beam irradiation results are presented. The processor demonstrates correct recovery, resuming program operation, from over 500 detected soft-errors, with no unrecoverable errors.",
author = "Chad Farnsworth and Clark, {Lawrence T.} and Gogulamudi, {Anudeep R.} and Vinay Vashishtha and Aditya Gujja",
year = "2016",
month = "7",
day = "18",
doi = "10.1109/TNS.2016.2540619",
language = "English (US)",
journal = "IEEE Transactions on Nuclear Science",
issn = "0018-9499",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - A Soft-Error Mitigated Microprocessor With Software Controlled Error Reporting and Recovery

AU - Farnsworth, Chad

AU - Clark, Lawrence T.

AU - Gogulamudi, Anudeep R.

AU - Vashishtha, Vinay

AU - Gujja, Aditya

PY - 2016/7/18

Y1 - 2016/7/18

N2 - A MIPS 4Kc compliant embedded microprocessor design that incorporates architectural features for software controlled soft-error recovery is presented. The design leverages classical fault tolerance techniques, e.g., error detection and instruction restart, implemented at the micro-architectural level, and added instructions for error recovery. Soft-errors are detected as the instructions commit to architectural state. At this point, an exception is taken and software recovers the correct machine state and restarts execution. The software recovery allows full machine inspection to determine error root causes. Added instructions also facilitate silicon validation of the hardware and software recovery mechanisms. The design is implemented in a commercial low standby power 90-nm bulk CMOS process and the prototype operates at up to 336 MHz. Finally, proton broad beam irradiation results are presented. The processor demonstrates correct recovery, resuming program operation, from over 500 detected soft-errors, with no unrecoverable errors.

AB - A MIPS 4Kc compliant embedded microprocessor design that incorporates architectural features for software controlled soft-error recovery is presented. The design leverages classical fault tolerance techniques, e.g., error detection and instruction restart, implemented at the micro-architectural level, and added instructions for error recovery. Soft-errors are detected as the instructions commit to architectural state. At this point, an exception is taken and software recovers the correct machine state and restarts execution. The software recovery allows full machine inspection to determine error root causes. Added instructions also facilitate silicon validation of the hardware and software recovery mechanisms. The design is implemented in a commercial low standby power 90-nm bulk CMOS process and the prototype operates at up to 336 MHz. Finally, proton broad beam irradiation results are presented. The processor demonstrates correct recovery, resuming program operation, from over 500 detected soft-errors, with no unrecoverable errors.

UR - http://www.scopus.com/inward/record.url?scp=84978790792&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84978790792&partnerID=8YFLogxK

U2 - 10.1109/TNS.2016.2540619

DO - 10.1109/TNS.2016.2540619

M3 - Article

AN - SCOPUS:84978790792

JO - IEEE Transactions on Nuclear Science

JF - IEEE Transactions on Nuclear Science

SN - 0018-9499

ER -