A Soft-Error Mitigated Microprocessor with Software Controlled Error Reporting and Recovery

Chad Farnsworth; Lawrence T. Clark; Anudeep R. Gogulamudi; Vinay Vashishtha; Aditya Gujja

doi:10.1109/TNS.2016.2540619

A Soft-Error Mitigated Microprocessor with Software Controlled Error Reporting and Recovery

Chad Farnsworth, Lawrence T. Clark, Anudeep R. Gogulamudi, Vinay Vashishtha, Aditya Gujja

Research output: Contribution to journal › Article › peer-review

9 Scopus citations

Abstract

A MIPS 4Kc compliant embedded microprocessor design that incorporates architectural features for software controlled soft-error recovery is presented. The design leverages classical fault tolerance techniques, e.g., error detection and instruction restart, implemented at the micro-architectural level, and added instructions for error recovery. Soft-errors are detected as the instructions commit to architectural state. At this point, an exception is taken and software recovers the correct machine state and restarts execution. The software recovery allows full machine inspection to determine error root causes. Added instructions also facilitate silicon validation of the hardware and software recovery mechanisms. The design is implemented in a commercial low standby power 90-nm bulk CMOS process and the prototype operates at up to 336 MHz. Finally, proton broad beam irradiation results are presented. The processor demonstrates correct recovery, resuming program operation, from over 500 detected soft-errors, with no unrecoverable errors.

Original language	English (US)
Article number	7514922
Pages (from-to)	2241-2249
Number of pages	9
Journal	IEEE Transactions on Nuclear Science
Volume	63
Issue number	4
DOIs	https://doi.org/10.1109/TNS.2016.2540619
State	Published - Aug 2016

Keywords

Microprocessor architecture
radiation hardening
single event effects
soft-errors

ASJC Scopus subject areas

Nuclear and High Energy Physics
Nuclear Energy and Engineering
Electrical and Electronic Engineering

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10.1109/TNS.2016.2540619

Cite this

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title = "A Soft-Error Mitigated Microprocessor with Software Controlled Error Reporting and Recovery",

abstract = "A MIPS 4Kc compliant embedded microprocessor design that incorporates architectural features for software controlled soft-error recovery is presented. The design leverages classical fault tolerance techniques, e.g., error detection and instruction restart, implemented at the micro-architectural level, and added instructions for error recovery. Soft-errors are detected as the instructions commit to architectural state. At this point, an exception is taken and software recovers the correct machine state and restarts execution. The software recovery allows full machine inspection to determine error root causes. Added instructions also facilitate silicon validation of the hardware and software recovery mechanisms. The design is implemented in a commercial low standby power 90-nm bulk CMOS process and the prototype operates at up to 336 MHz. Finally, proton broad beam irradiation results are presented. The processor demonstrates correct recovery, resuming program operation, from over 500 detected soft-errors, with no unrecoverable errors.",

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AU - Gujja, Aditya

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AB - A MIPS 4Kc compliant embedded microprocessor design that incorporates architectural features for software controlled soft-error recovery is presented. The design leverages classical fault tolerance techniques, e.g., error detection and instruction restart, implemented at the micro-architectural level, and added instructions for error recovery. Soft-errors are detected as the instructions commit to architectural state. At this point, an exception is taken and software recovers the correct machine state and restarts execution. The software recovery allows full machine inspection to determine error root causes. Added instructions also facilitate silicon validation of the hardware and software recovery mechanisms. The design is implemented in a commercial low standby power 90-nm bulk CMOS process and the prototype operates at up to 336 MHz. Finally, proton broad beam irradiation results are presented. The processor demonstrates correct recovery, resuming program operation, from over 500 detected soft-errors, with no unrecoverable errors.

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A Soft-Error Mitigated Microprocessor with Software Controlled Error Reporting and Recovery

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Keywords

ASJC Scopus subject areas

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