A soft-error hardened process portable embedded microprocessor

Vinay Vashishtha; Lawrence T. Clark; Srivatsan Chellappa; Anudeep R. Gogulamudi; Aditya Gujja; Chad Farnsworth

doi:10.1109/CICC.2015.7338366

A soft-error hardened process portable embedded microprocessor

Vinay Vashishtha, Lawrence T. Clark, Srivatsan Chellappa, Anudeep R. Gogulamudi, Aditya Gujja, Chad Farnsworth

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

An embedded microprocessor core designed to have high soft-error immunity is presented. The design achieves hardness via architectural, micro-architectural, and circuit techniques. The basis of the machine is a dual-redundant speculative pipeline that detects mismatches at their commission to architectural state. Added instructions allow software controlled recovery and restart of upset instructions. Key architectural state is stored in triple-mode redundant, self-correcting logic. Special automated place and route flows afford robustness against multiple node charge collection. Full clock gating allows low power, while redundant clocks mitigate clock upset induced errors. Register file based caches allow near-threshold low voltage operation. The design is implemented on a commercial 90-nm bulk CMOS process. Silicon results, including error correction examples, are presented.

Original language	English (US)
Title of host publication	Proceedings of the Custom Integrated Circuits Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Volume	2015-November
ISBN (Print)	9781479986828
DOIs	https://doi.org/10.1109/CICC.2015.7338366
State	Published - Nov 25 2015
Event	IEEE Custom Integrated Circuits Conference, CICC 2015 - San Jose, United States Duration: Sep 28 2015 → Sep 30 2015

Other

Other	IEEE Custom Integrated Circuits Conference, CICC 2015
Country/Territory	United States
City	San Jose
Period	9/28/15 → 9/30/15

Keywords

microprocessor architecture
Radiation hardening
single event effects
soft-errors

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2015.7338366

Cite this

Vashishtha, V, Clark, LT, Chellappa, S, Gogulamudi, AR, Gujja, A & Farnsworth, C 2015, A soft-error hardened process portable embedded microprocessor. in Proceedings of the Custom Integrated Circuits Conference. vol. 2015-November, 7338366, Institute of Electrical and Electronics Engineers Inc., IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, United States, 9/28/15. https://doi.org/10.1109/CICC.2015.7338366

@inproceedings{22d6e8fcf0ab48d5b3c947e38d28863d,

title = "A soft-error hardened process portable embedded microprocessor",

abstract = "An embedded microprocessor core designed to have high soft-error immunity is presented. The design achieves hardness via architectural, micro-architectural, and circuit techniques. The basis of the machine is a dual-redundant speculative pipeline that detects mismatches at their commission to architectural state. Added instructions allow software controlled recovery and restart of upset instructions. Key architectural state is stored in triple-mode redundant, self-correcting logic. Special automated place and route flows afford robustness against multiple node charge collection. Full clock gating allows low power, while redundant clocks mitigate clock upset induced errors. Register file based caches allow near-threshold low voltage operation. The design is implemented on a commercial 90-nm bulk CMOS process. Silicon results, including error correction examples, are presented.",

keywords = "microprocessor architecture, Radiation hardening, single event effects, soft-errors",

author = "Vinay Vashishtha and Clark, {Lawrence T.} and Srivatsan Chellappa and Gogulamudi, {Anudeep R.} and Aditya Gujja and Chad Farnsworth",

year = "2015",

month = nov,

day = "25",

doi = "10.1109/CICC.2015.7338366",

language = "English (US)",

isbn = "9781479986828",

volume = "2015-November",

booktitle = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE Custom Integrated Circuits Conference, CICC 2015 ; Conference date: 28-09-2015 Through 30-09-2015",

}

TY - GEN

T1 - A soft-error hardened process portable embedded microprocessor

AU - Vashishtha, Vinay

AU - Clark, Lawrence T.

AU - Chellappa, Srivatsan

AU - Gogulamudi, Anudeep R.

AU - Gujja, Aditya

AU - Farnsworth, Chad

PY - 2015/11/25

Y1 - 2015/11/25

N2 - An embedded microprocessor core designed to have high soft-error immunity is presented. The design achieves hardness via architectural, micro-architectural, and circuit techniques. The basis of the machine is a dual-redundant speculative pipeline that detects mismatches at their commission to architectural state. Added instructions allow software controlled recovery and restart of upset instructions. Key architectural state is stored in triple-mode redundant, self-correcting logic. Special automated place and route flows afford robustness against multiple node charge collection. Full clock gating allows low power, while redundant clocks mitigate clock upset induced errors. Register file based caches allow near-threshold low voltage operation. The design is implemented on a commercial 90-nm bulk CMOS process. Silicon results, including error correction examples, are presented.

AB - An embedded microprocessor core designed to have high soft-error immunity is presented. The design achieves hardness via architectural, micro-architectural, and circuit techniques. The basis of the machine is a dual-redundant speculative pipeline that detects mismatches at their commission to architectural state. Added instructions allow software controlled recovery and restart of upset instructions. Key architectural state is stored in triple-mode redundant, self-correcting logic. Special automated place and route flows afford robustness against multiple node charge collection. Full clock gating allows low power, while redundant clocks mitigate clock upset induced errors. Register file based caches allow near-threshold low voltage operation. The design is implemented on a commercial 90-nm bulk CMOS process. Silicon results, including error correction examples, are presented.

KW - microprocessor architecture

KW - Radiation hardening

KW - single event effects

KW - soft-errors

UR - http://www.scopus.com/inward/record.url?scp=84959233908&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84959233908&partnerID=8YFLogxK

U2 - 10.1109/CICC.2015.7338366

DO - 10.1109/CICC.2015.7338366

M3 - Conference contribution

AN - SCOPUS:84959233908

SN - 9781479986828

VL - 2015-November

BT - Proceedings of the Custom Integrated Circuits Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE Custom Integrated Circuits Conference, CICC 2015

Y2 - 28 September 2015 through 30 September 2015

ER -

A soft-error hardened process portable embedded microprocessor

Abstract

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Keywords

ASJC Scopus subject areas

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