TY - GEN
T1 - A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV and SRAM PUF for Authentication and Secret Key Generation
AU - Cherupally, Sai Kiran
AU - Yin, Shihui
AU - Kadetotad, Deepak
AU - Bae, Chisung
AU - Kim, Sang Joon
AU - Seo, Jae Sun
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/11
Y1 - 2019/11
N2 - We present a smart hardware security engine that combines three different sources of entropy, electrocardiogram (ECG), heart rate variability (HRV) and SRAM-based physical unclonable function (PUF), to perform real-time authentication and generate unique and random signatures. Such hybrid signatures vary person-to-person, device-to-device, and over time, and hence can be used for personal device authentication as well as secret random key generation, significantly reducing the scope of an attack. The prototype chip fabricated in 65nm LP CMOS consumes 4.04 μW at 0.6 V for real-time authentication. Compared to ECG-only authentication, the equal error rate of multi-source authentication is reduced by 18.9X down to 0.09% for an in-house ECG database. 256-bit secret keys generated by optimally combining ECG, HRV and PUF values pass NIST randomness tests with 100% pass rate.
AB - We present a smart hardware security engine that combines three different sources of entropy, electrocardiogram (ECG), heart rate variability (HRV) and SRAM-based physical unclonable function (PUF), to perform real-time authentication and generate unique and random signatures. Such hybrid signatures vary person-to-person, device-to-device, and over time, and hence can be used for personal device authentication as well as secret random key generation, significantly reducing the scope of an attack. The prototype chip fabricated in 65nm LP CMOS consumes 4.04 μW at 0.6 V for real-time authentication. Compared to ECG-only authentication, the equal error rate of multi-source authentication is reduced by 18.9X down to 0.09% for an in-house ECG database. 256-bit secret keys generated by optimally combining ECG, HRV and PUF values pass NIST randomness tests with 100% pass rate.
UR - http://www.scopus.com/inward/record.url?scp=85083640516&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85083640516&partnerID=8YFLogxK
U2 - 10.1109/A-SSCC47793.2019.9056922
DO - 10.1109/A-SSCC47793.2019.9056922
M3 - Conference contribution
AN - SCOPUS:85083640516
T3 - Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
SP - 145
EP - 148
BT - Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Y2 - 4 November 2019 through 6 November 2019
ER -