A self-evolving design methodology for power efficient multi-core systems

Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman Lysecky, Karthik Shankar, Janet Roveda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper introduces a new methodology that characterizes aging-duty cycle and aging-supply voltage relationships that are applicable to minimizing power consumption and task execution time to achieve low Bit-Energy-Ratio (BER). In contrast to the traditional workload balancing scheme where cores are regarded as homogeneous, we proposed a new task scheduler that ranks cores according to their various competitiveness evaluated based upon their reliability, temperature and timing requirements. Consequently, the new approach combines Internal characteristics (aging-duty cycle and aging-supply voltage curves) into an integrated framework to achieve system performance improvement or graceful degradation with high reliability and low power. Experimental results show that the proposed method has achieved 18% power reduction with about 4% performance degradation (in terms of accomplished workload) compared with traditional workload balancing methods.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Pages264-268
Number of pages5
DOIs
StatePublished - 2010
Event2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010 - San Jose, CA, United States
Duration: Nov 7 2010Nov 11 2010

Other

Other2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
CountryUnited States
CitySan Jose, CA
Period11/7/1011/11/10

Fingerprint

Aging of materials
Degradation
Electric potential
Electric power utilization
Temperature

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications
  • Software

Cite this

Sun, J., Zheng, R., Velamala, J., Cao, Y., Lysecky, R., Shankar, K., & Roveda, J. (2010). A self-evolving design methodology for power efficient multi-core systems. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD (pp. 264-268). [5654175] https://doi.org/10.1109/ICCAD.2010.5654175

A self-evolving design methodology for power efficient multi-core systems. / Sun, Jin; Zheng, Rui; Velamala, Jyothi; Cao, Yu; Lysecky, Roman; Shankar, Karthik; Roveda, Janet.

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2010. p. 264-268 5654175.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sun, J, Zheng, R, Velamala, J, Cao, Y, Lysecky, R, Shankar, K & Roveda, J 2010, A self-evolving design methodology for power efficient multi-core systems. in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD., 5654175, pp. 264-268, 2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, United States, 11/7/10. https://doi.org/10.1109/ICCAD.2010.5654175
Sun J, Zheng R, Velamala J, Cao Y, Lysecky R, Shankar K et al. A self-evolving design methodology for power efficient multi-core systems. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2010. p. 264-268. 5654175 https://doi.org/10.1109/ICCAD.2010.5654175
Sun, Jin ; Zheng, Rui ; Velamala, Jyothi ; Cao, Yu ; Lysecky, Roman ; Shankar, Karthik ; Roveda, Janet. / A self-evolving design methodology for power efficient multi-core systems. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2010. pp. 264-268
@inproceedings{b362cacbdd394e3abe3c71c9ec11ba23,
title = "A self-evolving design methodology for power efficient multi-core systems",
abstract = "This paper introduces a new methodology that characterizes aging-duty cycle and aging-supply voltage relationships that are applicable to minimizing power consumption and task execution time to achieve low Bit-Energy-Ratio (BER). In contrast to the traditional workload balancing scheme where cores are regarded as homogeneous, we proposed a new task scheduler that ranks cores according to their various competitiveness evaluated based upon their reliability, temperature and timing requirements. Consequently, the new approach combines Internal characteristics (aging-duty cycle and aging-supply voltage curves) into an integrated framework to achieve system performance improvement or graceful degradation with high reliability and low power. Experimental results show that the proposed method has achieved 18{\%} power reduction with about 4{\%} performance degradation (in terms of accomplished workload) compared with traditional workload balancing methods.",
author = "Jin Sun and Rui Zheng and Jyothi Velamala and Yu Cao and Roman Lysecky and Karthik Shankar and Janet Roveda",
year = "2010",
doi = "10.1109/ICCAD.2010.5654175",
language = "English (US)",
isbn = "9781424481927",
pages = "264--268",
booktitle = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD",

}

TY - GEN

T1 - A self-evolving design methodology for power efficient multi-core systems

AU - Sun, Jin

AU - Zheng, Rui

AU - Velamala, Jyothi

AU - Cao, Yu

AU - Lysecky, Roman

AU - Shankar, Karthik

AU - Roveda, Janet

PY - 2010

Y1 - 2010

N2 - This paper introduces a new methodology that characterizes aging-duty cycle and aging-supply voltage relationships that are applicable to minimizing power consumption and task execution time to achieve low Bit-Energy-Ratio (BER). In contrast to the traditional workload balancing scheme where cores are regarded as homogeneous, we proposed a new task scheduler that ranks cores according to their various competitiveness evaluated based upon their reliability, temperature and timing requirements. Consequently, the new approach combines Internal characteristics (aging-duty cycle and aging-supply voltage curves) into an integrated framework to achieve system performance improvement or graceful degradation with high reliability and low power. Experimental results show that the proposed method has achieved 18% power reduction with about 4% performance degradation (in terms of accomplished workload) compared with traditional workload balancing methods.

AB - This paper introduces a new methodology that characterizes aging-duty cycle and aging-supply voltage relationships that are applicable to minimizing power consumption and task execution time to achieve low Bit-Energy-Ratio (BER). In contrast to the traditional workload balancing scheme where cores are regarded as homogeneous, we proposed a new task scheduler that ranks cores according to their various competitiveness evaluated based upon their reliability, temperature and timing requirements. Consequently, the new approach combines Internal characteristics (aging-duty cycle and aging-supply voltage curves) into an integrated framework to achieve system performance improvement or graceful degradation with high reliability and low power. Experimental results show that the proposed method has achieved 18% power reduction with about 4% performance degradation (in terms of accomplished workload) compared with traditional workload balancing methods.

UR - http://www.scopus.com/inward/record.url?scp=78650923284&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78650923284&partnerID=8YFLogxK

U2 - 10.1109/ICCAD.2010.5654175

DO - 10.1109/ICCAD.2010.5654175

M3 - Conference contribution

AN - SCOPUS:78650923284

SN - 9781424481927

SP - 264

EP - 268

BT - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

ER -