A self-calibrated on-chip phase-noise-measurement circuit with -75dBc single-tone sensitivity at 100kHz offset

Waleed Khalil, Bertan Bakkaloglu, Sayfe Klaei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

An on-chip phase-noise-measurement circuit with single-tone measurement sensitivity of -75dBc at 100kHz offset from carrier is presented. The circuit uses a delay-line and mixer frequency discriminator and can operate up to 2GHz input frequency. This module does not rely on a reference clock and, with on-line self calibration, its accuracy is stabilized across gate-delay variations.

Original languageEnglish (US)
Title of host publication2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Pages546-547+621+537
DOIs
StatePublished - Sep 27 2007
Event54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
Duration: Feb 11 2007Feb 15 2007

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Other

Other54th IEEE International Solid-State Circuits Conference, ISSCC 2007
CountryUnited States
CitySan Francisco, CA
Period2/11/072/15/07

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Khalil, W., Bakkaloglu, B., & Klaei, S. (2007). A self-calibrated on-chip phase-noise-measurement circuit with -75dBc single-tone sensitivity at 100kHz offset. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 546-547+621+537). [4242507] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2007.373536