A self-biased operational transconductance amplifier in 0.18 micron 3D SOI-CMOS

Jennifer Blain Christen, Andreas G. Andreou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

We report on the design fabrication and testing of a wide range transconductance amplifier fabricated in the 0.18 μm MIT Lincoln Labs 3D SOI-CMOS process. The amplifier is designed to operate in subthreshold and employs self-biased cascode transistors to minimize the bias lines transversing the tiers in the technology.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages137-140
Number of pages4
StatePublished - 2007
Externally publishedYes
Event2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: May 27 2007May 30 2007

Other

Other2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
CountryUnited States
CityNew Orleans, LA
Period5/27/075/30/07

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A self-biased operational transconductance amplifier in 0.18 micron 3D SOI-CMOS'. Together they form a unique fingerprint.

Cite this