A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL in 40-nm CMOS

Yi Zhong; Shaolan Li; Arindam Sanyal; Xiyuan Tang; Linxiao Shen; Siliang Wu; Nan Sun

doi:10.1109/ASSCC.2018.8579255

A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL in 40-nm CMOS

Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, Nan Sun

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

This paper presents a power-efficient purely VCO-based 2 ^nd -order CT ΔΣ ADC featuring a modified DPLL structure. It combines a VCO with an SRO-based TDC, which enables 2 ^nd -order noise shaping without any OTA. The nonlinearity of the front-end VCO is mitigated by putting it inside a closed loop. A multi-PFD scheme reduces the VCO center frequency and power. The proposed architecture also realizes an intrinsic tri-level DWA. A prototype ADC in 40-nm CMOS process achieves a Schreier FoM of 170.3 dB with a DR of 72.7 dB over 5.2-MHz BW, while consuming 0.91 mW under 1.1-V supply.

Original language	English (US)
Title of host publication	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	93-94
Number of pages	2
ISBN (Electronic)	9781538664124
DOIs	https://doi.org/10.1109/ASSCC.2018.8579255
State	Published - Dec 14 2018
Externally published	Yes
Event	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Tainan, Taiwan, Province of China Duration: Nov 5 2018 → Nov 7 2018

Publication series

Name	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

Conference

Conference	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
Country/Territory	Taiwan, Province of China
City	Tainan
Period	11/5/18 → 11/7/18

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2018.8579255

Cite this

Zhong, Y., Li, S., Sanyal, A., Tang, X., Shen, L., Wu, S., & Sun, N. (2018). A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL in 40-nm CMOS. In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings (pp. 93-94). Article 8579255 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2018.8579255

A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL in 40-nm CMOS. / Zhong, Yi; Li, Shaolan; Sanyal, Arindam et al.
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 93-94 8579255 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhong, Y, Li, S, Sanyal, A, Tang, X, Shen, L, Wu, S & Sun, N 2018, A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL in 40-nm CMOS. in 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings., 8579255, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 93-94, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, Province of China, 11/5/18. https://doi.org/10.1109/ASSCC.2018.8579255

Zhong Y, Li S, Sanyal A, Tang X, Shen L, Wu S et al. A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL in 40-nm CMOS. In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 93-94. 8579255. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). doi: 10.1109/ASSCC.2018.8579255

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abstract = " This paper presents a power-efficient purely VCO-based 2 nd -order CT ΔΣ ADC featuring a modified DPLL structure. It combines a VCO with an SRO-based TDC, which enables 2 nd -order noise shaping without any OTA. The nonlinearity of the front-end VCO is mitigated by putting it inside a closed loop. A multi-PFD scheme reduces the VCO center frequency and power. The proposed architecture also realizes an intrinsic tri-level DWA. A prototype ADC in 40-nm CMOS process achieves a Schreier FoM of 170.3 dB with a DR of 72.7 dB over 5.2-MHz BW, while consuming 0.91 mW under 1.1-V supply. ",

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A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL in 40-nm CMOS

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