A scalable performance 32b microprocessor

L. T. Clark, E. Hoffman, M. Schaecher, M. Biyani, D. Roberts, Y. Liao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

A reduced instruction set computing (RISC) microprocessor was proposed using a six-layer metal 0.18 μm complementary metal oxide semiconductor (CMOS) process. The microprocessor consists of 32 kB instruction and data caches and an 8-entry coalescing writeback buffer. The design was implemented in static CMOS logic and supported full clock stop. Other important aspect of the microprocessor architecture was described in detail.

Original languageEnglish (US)
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages230-231
Number of pages2
StatePublished - 2001
Externally publishedYes
EventDigest of Technical Papers - IEEE International Solid-State Circuits Conference -
Duration: Feb 5 2001Feb 6 2001

Other

OtherDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Period2/5/012/6/01

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Clark, L. T., Hoffman, E., Schaecher, M., Biyani, M., Roberts, D., & Liao, Y. (2001). A scalable performance 32b microprocessor. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 230-231)