A scalable performance 32b microprocessor

L. T. Clark; E. Hoffman; M. Schaecher; M. Biyani; D. Roberts; Y. Liao

A scalable performance 32b microprocessor

L. T. Clark, E. Hoffman, M. Schaecher, M. Biyani, D. Roberts, Y. Liao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A reduced instruction set computing (RISC) microprocessor was proposed using a six-layer metal 0.18 μm complementary metal oxide semiconductor (CMOS) process. The microprocessor consists of 32 kB instruction and data caches and an 8-entry coalescing writeback buffer. The design was implemented in static CMOS logic and supported full clock stop. Other important aspect of the microprocessor architecture was described in detail.

Original language	English (US)
Title of host publication	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages	230-231
Number of pages	2
State	Published - 2001
Externally published	Yes
Event	Digest of Technical Papers - IEEE International Solid-State Circuits Conference - Duration: Feb 5 2001 → Feb 6 2001

Other

Other	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Period	2/5/01 → 2/6/01

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

@inproceedings{15ba06505c3443048e36281860f05d77,

title = "A scalable performance 32b microprocessor",

abstract = "A reduced instruction set computing (RISC) microprocessor was proposed using a six-layer metal 0.18 μm complementary metal oxide semiconductor (CMOS) process. The microprocessor consists of 32 kB instruction and data caches and an 8-entry coalescing writeback buffer. The design was implemented in static CMOS logic and supported full clock stop. Other important aspect of the microprocessor architecture was described in detail.",

author = "Clark, {L. T.} and E. Hoffman and M. Schaecher and M. Biyani and D. Roberts and Y. Liao",

year = "2001",

language = "English (US)",

pages = "230--231",

booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

note = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference ; Conference date: 05-02-2001 Through 06-02-2001",

}

TY - GEN

T1 - A scalable performance 32b microprocessor

AU - Clark, L. T.

AU - Hoffman, E.

AU - Schaecher, M.

AU - Biyani, M.

AU - Roberts, D.

AU - Liao, Y.

PY - 2001

Y1 - 2001

N2 - A reduced instruction set computing (RISC) microprocessor was proposed using a six-layer metal 0.18 μm complementary metal oxide semiconductor (CMOS) process. The microprocessor consists of 32 kB instruction and data caches and an 8-entry coalescing writeback buffer. The design was implemented in static CMOS logic and supported full clock stop. Other important aspect of the microprocessor architecture was described in detail.

AB - A reduced instruction set computing (RISC) microprocessor was proposed using a six-layer metal 0.18 μm complementary metal oxide semiconductor (CMOS) process. The microprocessor consists of 32 kB instruction and data caches and an 8-entry coalescing writeback buffer. The design was implemented in static CMOS logic and supported full clock stop. Other important aspect of the microprocessor architecture was described in detail.

UR - http://www.scopus.com/inward/record.url?scp=0035054822&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0035054822&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0035054822

SP - 230

EP - 231

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Y2 - 5 February 2001 through 6 February 2001

ER -

A scalable performance 32b microprocessor

Abstract

Other

ASJC Scopus subject areas

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