A robust, self-tuning CMOS circuit for built-in go/no-go testing of synthesizer phase noise

Erdem S. Erdogan, Suie Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

As one way of reducing the reliance on mixed signal testers for circuits with small analog content, researchers have proposed built-in self-test (BiST) techniques that target specific parameters of analog circuits. Most BiST techniques for phase locked loops (PLL) aim at measuring the timing jitter through precise on-chip clocks and/or additional computation of measured specs. In this paper, we propose a built-in test circuit to perform go/no-go testing for in-band PLL phase noise. Our circuit measures the band-limited, low frequency noise power at the input of the voltage controlled oscillator (VCO) which is translated as the high frequency phase noise at the output of the PLL. Our circuit contains a self calibration sequence based on a simple sinusoidal input to make it robust to process variations. The circuit is implemented using 0.8μm CMOS process with the equivalent area of roughly 800 2-input minimum size NAND gates. Monte Carlo simulations have confirmed that the test circuit can robustly detect noise levels that are above the specified fail level.

Original languageEnglish (US)
Title of host publication2006 IEEE International Test Conference, ITC
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)1424402921, 9781424402922
DOIs
StatePublished - Jan 1 2006
Externally publishedYes
Event2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States
Duration: Oct 22 2006Oct 27 2006

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Other

Other2006 IEEE International Test Conference, ITC
Country/TerritoryUnited States
CitySanta Clara, CA
Period10/22/0610/27/06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

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