TY - GEN
T1 - A robust, self-tuning CMOS circuit for built-in go/no-go testing of synthesizer phase noise
AU - Erdogan, Erdem S.
AU - Ozev, Sule
PY - 2006
Y1 - 2006
N2 - As one way of reducing the reliance on mixed signal testers for circuits with small analog content, researchers have proposed built-in self-test (BiST) techniques that target specific parameters of analog circuits. Most BiST techniques for phase locked loops (PLL) aim at measuring the timing jitter through precise on-chip clocks and/or additional computation of measured specs. In this paper, we propose a built-in test circuit to perform go/no-go testing for in-band PLL phase noise. Our circuit measures the band-limited, low frequency noise power at the input of the voltage controlled oscillator (VCO) which is translated as the high frequency phase noise at the output of the PLL. Our circuit contains a self calibration sequence based on a simple sinusoidal input to make it robust to process variations. The circuit is implemented using 0.8μm CMOS process with the equivalent area of roughly 800 2-input minimum size NAND gates. Monte Carlo simulations have confirmed that the test circuit can robustly detect noise levels that are above the specified fail level.
AB - As one way of reducing the reliance on mixed signal testers for circuits with small analog content, researchers have proposed built-in self-test (BiST) techniques that target specific parameters of analog circuits. Most BiST techniques for phase locked loops (PLL) aim at measuring the timing jitter through precise on-chip clocks and/or additional computation of measured specs. In this paper, we propose a built-in test circuit to perform go/no-go testing for in-band PLL phase noise. Our circuit measures the band-limited, low frequency noise power at the input of the voltage controlled oscillator (VCO) which is translated as the high frequency phase noise at the output of the PLL. Our circuit contains a self calibration sequence based on a simple sinusoidal input to make it robust to process variations. The circuit is implemented using 0.8μm CMOS process with the equivalent area of roughly 800 2-input minimum size NAND gates. Monte Carlo simulations have confirmed that the test circuit can robustly detect noise levels that are above the specified fail level.
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U2 - 10.1109/TEST.2006.297696
DO - 10.1109/TEST.2006.297696
M3 - Conference contribution
AN - SCOPUS:39749099910
SN - 1424402921
SN - 9781424402922
T3 - Proceedings - International Test Conference
BT - 2006 IEEE International Test Conference, ITC
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2006 IEEE International Test Conference, ITC
Y2 - 22 October 2006 through 27 October 2006
ER -