A Robust Edge-Triggered Threshold Logic Flipflop (PNAND) With Scan, Preset and Clear

Sarma Vrudhula (Inventor)

Research output: Patent

Abstract

Digital circuits use sequences of logic gates called flip-flops to store and transmit binary information. A NAND is a multi-input flip-flop that produces a false output only if all the inputs are true, allowing it to process any other logic function. A threshold logic flip-flop can compute a single input function like an ordinary D-type flip-flop, as well as multi-input functions that require complex circuit structures. As a result, digital circuits made from threshold logic flip-flops are smaller, faster, and more power-efficient. However, current threshold logic flip-flops have large clock (registry) load for a higher number of inputs, allowing variable loading that causes clock timing issues and have no failsafe to prevent the occurrence of a floating node (an undefined signal). Researchers at ASU have developed PNAND, a multi-input flip-flop circuit that computes a threshold logic function using differential (electromagnetic interference-resistant) signaling. PNAND eliminates the possibility of a floating node by applying positive feedback between two input signals, ensuring neither node falls into an undefined state. PNANDs input capacitance is substantially lower and independent of the input, reducing clock demand and minimizing timing variability. PNAND is less intrusive in terms of power and delay, and produces higher quality results when compared to traditional logic functions. Additionally, an asynchronous preset-and-clear mechanism can simultaneously set or reset all of PNANDs latches. Overall, PNANDs ability to compute complex logic functions with little to no error alongside an efficient scan, preset, and clear function make it a terrific contender in the digital circuit and microelectronic industry. Potential Applications Digital Circuits DSP Cores Microelectronics Microprocessors Benefits and Advantages Accurate Failsafe ensures that there is no soft error (incorrect signal) Less intrusive scan functionality allows superior quality control Efficient Low input capacitance reduces power consumption without penalizing performance, resulting in smaller, faster circuits Effective - Computes simple or complex, single or multi-input logic functions Asynchronous preset-and-clear simultaneously sets or resets all latches Reliable Withstands electromagnetic interference through differential signaling Download Original PDF For more information about the inventor(s) and their research, please see: Dr. Sarma Vrudhula's directory webpage For more information about related technologies, please see: M15-005P: Robust, Edge-Triggered Threshold Logic PNAND Flip-Flop With Scan, Preset & Clear Functionality
Original languageEnglish (US)
StatePublished - Mar 23 2015

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