A robust edge encoding technique for energy-efficient multi-cycle interconnect

Jae Sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2V 65nm CMOS technology, the approach achieves up to 31% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance reductions. The technique further reduces energy consumption by 38% with iso-throughput at the expense of one-cycle latency. Energy savings are shown to be more robust to process variations than previous techniques.

Original languageEnglish (US)
Title of host publicationISLPED'07
Subtitle of host publicationProceedings of the 2007 International Symposium on Low Power Electronics and Design
Pages68-73
Number of pages6
DOIs
StatePublished - Dec 17 2007
Externally publishedYes
EventISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR, United States
Duration: Aug 27 2007Aug 29 2007

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

OtherISLPED'07: 2007 International Symposium on Low Power Electronics and Design
CountryUnited States
CityPortland, OR
Period8/27/078/29/07

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Keywords

  • Encoding
  • Interconnect
  • Multi-cycle interconnect
  • Repeaters

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Seo, J. S., Sylvester, D., Blaauw, D., Kaul, H., & Krishnamurthy, R. (2007). A robust edge encoding technique for energy-efficient multi-cycle interconnect. In ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design (pp. 68-73). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/1283780.1283796