A robust edge encoding technique for energy-efficient multi-cycle interconnect

Jae Sun Seo; Dennis Sylvester; David Blaauw; Himanshu Kaul; Ram Krishnamurthy

doi:10.1145/1283780.1283796

A robust edge encoding technique for energy-efficient multi-cycle interconnect

Jae Sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2V 65nm CMOS technology, the approach achieves up to 31% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance reductions. The technique further reduces energy consumption by 38% with iso-throughput at the expense of one-cycle latency. Energy savings are shown to be more robust to process variations than previous techniques.

Original language	English (US)
Title of host publication	ISLPED'07
Subtitle of host publication	Proceedings of the 2007 International Symposium on Low Power Electronics and Design
Pages	68-73
Number of pages	6
DOIs	https://doi.org/10.1145/1283780.1283796
State	Published - 2007
Externally published	Yes
Event	ISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR, United States Duration: Aug 27 2007 → Aug 29 2007

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	ISLPED'07: 2007 International Symposium on Low Power Electronics and Design
Country/Territory	United States
City	Portland, OR
Period	8/27/07 → 8/29/07

Keywords

Encoding
Interconnect
Multi-cycle interconnect
Repeaters

ASJC Scopus subject areas

General Engineering

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10.1145/1283780.1283796

Cite this

Seo, J. S., Sylvester, D., Blaauw, D., Kaul, H., & Krishnamurthy, R. (2007). A robust edge encoding technique for energy-efficient multi-cycle interconnect. In ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design (pp. 68-73). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/1283780.1283796

A robust edge encoding technique for energy-efficient multi-cycle interconnect. / Seo, Jae Sun; Sylvester, Dennis; Blaauw, David et al.
ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. 2007. p. 68-73 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Seo, JS, Sylvester, D, Blaauw, D, Kaul, H & Krishnamurthy, R 2007, A robust edge encoding technique for energy-efficient multi-cycle interconnect. in ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, pp. 68-73, ISLPED'07: 2007 International Symposium on Low Power Electronics and Design, Portland, OR, United States, 8/27/07. https://doi.org/10.1145/1283780.1283796

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AB - In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2V 65nm CMOS technology, the approach achieves up to 31% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance reductions. The technique further reduces energy consumption by 38% with iso-throughput at the expense of one-cycle latency. Energy savings are shown to be more robust to process variations than previous techniques.

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KW - Repeaters

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A robust edge encoding technique for energy-efficient multi-cycle interconnect

Abstract

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Keywords

ASJC Scopus subject areas

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