A resilience roadmap

Sani R. Nassif; Nikil Mehta; Yu Cao

doi:10.1109/date.2010.5456958

A resilience roadmap

Sani R. Nassif, Nikil Mehta, Yu Cao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

76 Scopus citations

Abstract

Technology scaling has an increasing impact on the resilience of CMOS circuits. This outcome is the result of (a) increasing sensitivity to various intrinsic and extrinsic noise sources as circuits shrink, and (b) a corresponding increase in parametric variability causing behavior similar to what would be expected with hard (topological) faults. This paper examines the issue of circuit resilience, then proposes and demonstrates a roadmap for evaluating fault rates starting at the 45nm and going down to the 12nm nodes. The complete infrastructure necessary to make these predictions is placed in the open source domain, with the hope that it will invigorate research in this area.

Original language	English (US)
Title of host publication	DATE 10 - Design, Automation and Test in Europe
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1011-1016
Number of pages	6
ISBN (Print)	9783981080162
DOIs	https://doi.org/10.1109/date.2010.5456958
State	Published - Jan 1 2010
Event	Design, Automation and Test in Europe Conference and Exhibition, DATE 2010 - Dresden, Germany Duration: Mar 8 2010 → Mar 12 2010

Publication series

Name	Proceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)	1530-1591

Other

Other	Design, Automation and Test in Europe Conference and Exhibition, DATE 2010
Country/Territory	Germany
City	Dresden
Period	3/8/10 → 3/12/10

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/date.2010.5456958

Cite this

Nassif, SR, Mehta, N & Cao, Y 2010, A resilience roadmap. in DATE 10 - Design, Automation and Test in Europe., 5456958, Proceedings -Design, Automation and Test in Europe, DATE, Institute of Electrical and Electronics Engineers Inc., pp. 1011-1016, Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, Dresden, Germany, 3/8/10. https://doi.org/10.1109/date.2010.5456958

@inproceedings{1280e6ea62d64e4eb2a059e4b2af4709,

title = "A resilience roadmap",

abstract = "Technology scaling has an increasing impact on the resilience of CMOS circuits. This outcome is the result of (a) increasing sensitivity to various intrinsic and extrinsic noise sources as circuits shrink, and (b) a corresponding increase in parametric variability causing behavior similar to what would be expected with hard (topological) faults. This paper examines the issue of circuit resilience, then proposes and demonstrates a roadmap for evaluating fault rates starting at the 45nm and going down to the 12nm nodes. The complete infrastructure necessary to make these predictions is placed in the open source domain, with the hope that it will invigorate research in this area.",

author = "Nassif, {Sani R.} and Nikil Mehta and Yu Cao",

year = "2010",

month = jan,

day = "1",

doi = "10.1109/date.2010.5456958",

language = "English (US)",

isbn = "9783981080162",

series = "Proceedings -Design, Automation and Test in Europe, DATE",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1011--1016",

booktitle = "DATE 10 - Design, Automation and Test in Europe",

note = "Design, Automation and Test in Europe Conference and Exhibition, DATE 2010 ; Conference date: 08-03-2010 Through 12-03-2010",

}

TY - GEN

T1 - A resilience roadmap

AU - Nassif, Sani R.

AU - Mehta, Nikil

AU - Cao, Yu

PY - 2010/1/1

Y1 - 2010/1/1

N2 - Technology scaling has an increasing impact on the resilience of CMOS circuits. This outcome is the result of (a) increasing sensitivity to various intrinsic and extrinsic noise sources as circuits shrink, and (b) a corresponding increase in parametric variability causing behavior similar to what would be expected with hard (topological) faults. This paper examines the issue of circuit resilience, then proposes and demonstrates a roadmap for evaluating fault rates starting at the 45nm and going down to the 12nm nodes. The complete infrastructure necessary to make these predictions is placed in the open source domain, with the hope that it will invigorate research in this area.

AB - Technology scaling has an increasing impact on the resilience of CMOS circuits. This outcome is the result of (a) increasing sensitivity to various intrinsic and extrinsic noise sources as circuits shrink, and (b) a corresponding increase in parametric variability causing behavior similar to what would be expected with hard (topological) faults. This paper examines the issue of circuit resilience, then proposes and demonstrates a roadmap for evaluating fault rates starting at the 45nm and going down to the 12nm nodes. The complete infrastructure necessary to make these predictions is placed in the open source domain, with the hope that it will invigorate research in this area.

UR - http://www.scopus.com/inward/record.url?scp=77953099455&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77953099455&partnerID=8YFLogxK

U2 - 10.1109/date.2010.5456958

DO - 10.1109/date.2010.5456958

M3 - Conference contribution

AN - SCOPUS:77953099455

SN - 9783981080162

T3 - Proceedings -Design, Automation and Test in Europe, DATE

SP - 1011

EP - 1016

BT - DATE 10 - Design, Automation and Test in Europe

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - Design, Automation and Test in Europe Conference and Exhibition, DATE 2010

Y2 - 8 March 2010 through 12 March 2010

ER -

A resilience roadmap

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this