A radiation hardened by design register file with lightweight error detection and correction

Karl C. Mohr, Giby Samson, Lawrence T. Clark

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

A radiation hardened by design 32 × 36 b register file with error detection and correction (EDAC) capability is presented. The lightweight EDAC scheme (LEDAC) supports fine granularity (byte) writes, with low area and latency overhead, suitable for small, fast memories such as register file and first-level cache memory. The LEDAC scheme is described and its impact on memory efficiency and speed are quantified. The register file has been tested to be functional on a foundry 0.13 μm bulk CMOS process with a measured speed over 1 GHz at VDD = 1.5 V. The LEDAC scheme is implemented in an external FPGA. Accelerated heavy ion testing results are also described. The experimentally measured RHBD register file SEE behavior is examined, and the proposed LEDAC scheme is shown to alleviate all soft errors in accelerated testing.

Original languageEnglish (US)
Pages (from-to)1335-1342
Number of pages8
JournalIEEE Transactions on Nuclear Science
Volume54
Issue number4
DOIs
StatePublished - Aug 2007

Fingerprint

Error detection
registers
Error correction
files
Radiation
Data storage equipment
Cache memory
Testing
Foundries
radiation
Heavy ions
Field programmable gate arrays (FPGA)
programming environments
foundries
CMOS
heavy ions

Keywords

  • Error detection and correction (EDAC)
  • Radiation hardening
  • Register file

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Nuclear Energy and Engineering

Cite this

A radiation hardened by design register file with lightweight error detection and correction. / Mohr, Karl C.; Samson, Giby; Clark, Lawrence T.

In: IEEE Transactions on Nuclear Science, Vol. 54, No. 4, 08.2007, p. 1335-1342.

Research output: Contribution to journalArticle

Mohr, Karl C. ; Samson, Giby ; Clark, Lawrence T. / A radiation hardened by design register file with lightweight error detection and correction. In: IEEE Transactions on Nuclear Science. 2007 ; Vol. 54, No. 4. pp. 1335-1342.
@article{28135768cdd84fb29769e230b033a9de,
title = "A radiation hardened by design register file with lightweight error detection and correction",
abstract = "A radiation hardened by design 32 × 36 b register file with error detection and correction (EDAC) capability is presented. The lightweight EDAC scheme (LEDAC) supports fine granularity (byte) writes, with low area and latency overhead, suitable for small, fast memories such as register file and first-level cache memory. The LEDAC scheme is described and its impact on memory efficiency and speed are quantified. The register file has been tested to be functional on a foundry 0.13 μm bulk CMOS process with a measured speed over 1 GHz at VDD = 1.5 V. The LEDAC scheme is implemented in an external FPGA. Accelerated heavy ion testing results are also described. The experimentally measured RHBD register file SEE behavior is examined, and the proposed LEDAC scheme is shown to alleviate all soft errors in accelerated testing.",
keywords = "Error detection and correction (EDAC), Radiation hardening, Register file",
author = "Mohr, {Karl C.} and Giby Samson and Clark, {Lawrence T.}",
year = "2007",
month = "8",
doi = "10.1109/TNS.2007.903173",
language = "English (US)",
volume = "54",
pages = "1335--1342",
journal = "IEEE Transactions on Nuclear Science",
issn = "0018-9499",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

TY - JOUR

T1 - A radiation hardened by design register file with lightweight error detection and correction

AU - Mohr, Karl C.

AU - Samson, Giby

AU - Clark, Lawrence T.

PY - 2007/8

Y1 - 2007/8

N2 - A radiation hardened by design 32 × 36 b register file with error detection and correction (EDAC) capability is presented. The lightweight EDAC scheme (LEDAC) supports fine granularity (byte) writes, with low area and latency overhead, suitable for small, fast memories such as register file and first-level cache memory. The LEDAC scheme is described and its impact on memory efficiency and speed are quantified. The register file has been tested to be functional on a foundry 0.13 μm bulk CMOS process with a measured speed over 1 GHz at VDD = 1.5 V. The LEDAC scheme is implemented in an external FPGA. Accelerated heavy ion testing results are also described. The experimentally measured RHBD register file SEE behavior is examined, and the proposed LEDAC scheme is shown to alleviate all soft errors in accelerated testing.

AB - A radiation hardened by design 32 × 36 b register file with error detection and correction (EDAC) capability is presented. The lightweight EDAC scheme (LEDAC) supports fine granularity (byte) writes, with low area and latency overhead, suitable for small, fast memories such as register file and first-level cache memory. The LEDAC scheme is described and its impact on memory efficiency and speed are quantified. The register file has been tested to be functional on a foundry 0.13 μm bulk CMOS process with a measured speed over 1 GHz at VDD = 1.5 V. The LEDAC scheme is implemented in an external FPGA. Accelerated heavy ion testing results are also described. The experimentally measured RHBD register file SEE behavior is examined, and the proposed LEDAC scheme is shown to alleviate all soft errors in accelerated testing.

KW - Error detection and correction (EDAC)

KW - Radiation hardening

KW - Register file

UR - http://www.scopus.com/inward/record.url?scp=34548057465&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34548057465&partnerID=8YFLogxK

U2 - 10.1109/TNS.2007.903173

DO - 10.1109/TNS.2007.903173

M3 - Article

VL - 54

SP - 1335

EP - 1342

JO - IEEE Transactions on Nuclear Science

JF - IEEE Transactions on Nuclear Science

SN - 0018-9499

IS - 4

ER -