A radiation hardened by design register file with lightweight error detection and correction

Karl C. Mohr; Giby Samson; Lawrence T. Clark

doi:10.1109/TNS.2007.903173

A radiation hardened by design register file with lightweight error detection and correction

Karl C. Mohr, Giby Samson, Lawrence T. Clark

Research output: Contribution to journal › Article › peer-review

13 Scopus citations

Abstract

A radiation hardened by design 32 × 36 b register file with error detection and correction (EDAC) capability is presented. The lightweight EDAC scheme (LEDAC) supports fine granularity (byte) writes, with low area and latency overhead, suitable for small, fast memories such as register file and first-level cache memory. The LEDAC scheme is described and its impact on memory efficiency and speed are quantified. The register file has been tested to be functional on a foundry 0.13 μm bulk CMOS process with a measured speed over 1 GHz at V_DD = 1.5 V. The LEDAC scheme is implemented in an external FPGA. Accelerated heavy ion testing results are also described. The experimentally measured RHBD register file SEE behavior is examined, and the proposed LEDAC scheme is shown to alleviate all soft errors in accelerated testing.

Original language	English (US)
Pages (from-to)	1335-1342
Number of pages	8
Journal	IEEE Transactions on Nuclear Science
Volume	54
Issue number	4
DOIs	https://doi.org/10.1109/TNS.2007.903173
State	Published - Aug 2007

Keywords

Error detection and correction (EDAC)
Radiation hardening
Register file

ASJC Scopus subject areas

Nuclear and High Energy Physics
Nuclear Energy and Engineering
Electrical and Electronic Engineering

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10.1109/TNS.2007.903173

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abstract = "A radiation hardened by design 32 × 36 b register file with error detection and correction (EDAC) capability is presented. The lightweight EDAC scheme (LEDAC) supports fine granularity (byte) writes, with low area and latency overhead, suitable for small, fast memories such as register file and first-level cache memory. The LEDAC scheme is described and its impact on memory efficiency and speed are quantified. The register file has been tested to be functional on a foundry 0.13 μm bulk CMOS process with a measured speed over 1 GHz at VDD = 1.5 V. The LEDAC scheme is implemented in an external FPGA. Accelerated heavy ion testing results are also described. The experimentally measured RHBD register file SEE behavior is examined, and the proposed LEDAC scheme is shown to alleviate all soft errors in accelerated testing.",

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note = "Funding Information: Manuscript received January 15, 2007; revised April 24, 2007 and June 7, 2007. This work was supported by the USAF/VSSE, Albuquerque, NM, under contract F29601-02-2-299. The authors are with the Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: karl.mohr@asu.edu; gibs@asu.edu; lawrence.clark@asu.edu). Digital Object Identifier 10.1109/TNS.2007.903173",

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AU - Samson, Giby

AU - Clark, Lawrence T.

N1 - Funding Information: Manuscript received January 15, 2007; revised April 24, 2007 and June 7, 2007. This work was supported by the USAF/VSSE, Albuquerque, NM, under contract F29601-02-2-299. The authors are with the Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: karl.mohr@asu.edu; gibs@asu.edu; lawrence.clark@asu.edu). Digital Object Identifier 10.1109/TNS.2007.903173

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AB - A radiation hardened by design 32 × 36 b register file with error detection and correction (EDAC) capability is presented. The lightweight EDAC scheme (LEDAC) supports fine granularity (byte) writes, with low area and latency overhead, suitable for small, fast memories such as register file and first-level cache memory. The LEDAC scheme is described and its impact on memory efficiency and speed are quantified. The register file has been tested to be functional on a foundry 0.13 μm bulk CMOS process with a measured speed over 1 GHz at VDD = 1.5 V. The LEDAC scheme is implemented in an external FPGA. Accelerated heavy ion testing results are also described. The experimentally measured RHBD register file SEE behavior is examined, and the proposed LEDAC scheme is shown to alleviate all soft errors in accelerated testing.

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A radiation hardened by design register file with lightweight error detection and correction

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Keywords

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