A predictable and command-level priority-based DRAM controller for mixed-criticality systems

Hokeun Kim, David Bromany, Edward A. Lee, Michael Zimmer, Aviral Shrivastava, Junkwang Oh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)

Abstract

Mixed-criticality systems have tasks with different criticality levels running on the same hardware platform. Today's DRAM controllers cannot adequately satisfy the often conflicting requirements of tightly bounded worst-case latency for critical tasks and high performance for non-critical real-time tasks. We propose a DRAM memory controller that meets these requirements by using bank-aware address mapping and DRAM command-level priority-based scheduling with preemption. Many standard DRAM controllers can be extended with our approach, incurring no performance penalty when critical tasks are not generating DRAM requests. Our approach is evaluated by replaying memory traces obtained from executing benchmarks on an ARM ISA-based processor with caches, which is simulated on the gem5 architecture simulator. We compare our approach against previous TDM-based approaches, showing that our proposed memory controller achieves dramatically higher performance for non-critical tasks, without any significant impact on the worstcase latency of critical tasks.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages317-326
Number of pages10
Volume2015-May
ISBN (Print)9781479986033
DOIs
StatePublished - May 14 2015
Event21st IEEE Real Time and Embedded Technology and Applications Symposium, RTAS 2015 - Seattle, United States
Duration: Apr 13 2015Apr 16 2015

Other

Other21st IEEE Real Time and Embedded Technology and Applications Symposium, RTAS 2015
CountryUnited States
CitySeattle
Period4/13/154/16/15

Fingerprint

Dynamic random access storage
Controllers
Data storage equipment
Time division multiplexing
Simulators
Scheduling
Hardware

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Kim, H., Bromany, D., Lee, E. A., Zimmer, M., Shrivastava, A., & Oh, J. (2015). A predictable and command-level priority-based DRAM controller for mixed-criticality systems. In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS (Vol. 2015-May, pp. 317-326). [7108455] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RTAS.2015.7108455

A predictable and command-level priority-based DRAM controller for mixed-criticality systems. / Kim, Hokeun; Bromany, David; Lee, Edward A.; Zimmer, Michael; Shrivastava, Aviral; Oh, Junkwang.

Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS. Vol. 2015-May Institute of Electrical and Electronics Engineers Inc., 2015. p. 317-326 7108455.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, H, Bromany, D, Lee, EA, Zimmer, M, Shrivastava, A & Oh, J 2015, A predictable and command-level priority-based DRAM controller for mixed-criticality systems. in Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS. vol. 2015-May, 7108455, Institute of Electrical and Electronics Engineers Inc., pp. 317-326, 21st IEEE Real Time and Embedded Technology and Applications Symposium, RTAS 2015, Seattle, United States, 4/13/15. https://doi.org/10.1109/RTAS.2015.7108455
Kim H, Bromany D, Lee EA, Zimmer M, Shrivastava A, Oh J. A predictable and command-level priority-based DRAM controller for mixed-criticality systems. In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS. Vol. 2015-May. Institute of Electrical and Electronics Engineers Inc. 2015. p. 317-326. 7108455 https://doi.org/10.1109/RTAS.2015.7108455
Kim, Hokeun ; Bromany, David ; Lee, Edward A. ; Zimmer, Michael ; Shrivastava, Aviral ; Oh, Junkwang. / A predictable and command-level priority-based DRAM controller for mixed-criticality systems. Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS. Vol. 2015-May Institute of Electrical and Electronics Engineers Inc., 2015. pp. 317-326
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