TY - GEN
T1 - A power and performance model for network-on-chip architectures
AU - Banerjee, Nilanjan
AU - Vellanki, Praveen
AU - Chatha, Karam S.
PY - 2004
Y1 - 2004
N2 - Networks-on-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Innovative system-level performance models are required for designing NoC based architectures. This paper presents a VHDL based cycle accurate register transfer level model for evaluating the latency, throughput, dynamic, and leakage power consumption of NoC based interconnection architectures. We implemented a parameterized register transfer level design of the NoC architecture elements. The design is parameterized on (i) size of packets, (ii) length and width of physical links, (Hi) number, and depth of virtual channels, and (iv) switching technique. The paper discusses in detail the architecture and characterization of the various NoC components. The paper presents results obtained by application of the model towards design space exploration, and power versus performance trade-off analysis of 4×4 mesh based NoC architecture.
AB - Networks-on-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Innovative system-level performance models are required for designing NoC based architectures. This paper presents a VHDL based cycle accurate register transfer level model for evaluating the latency, throughput, dynamic, and leakage power consumption of NoC based interconnection architectures. We implemented a parameterized register transfer level design of the NoC architecture elements. The design is parameterized on (i) size of packets, (ii) length and width of physical links, (Hi) number, and depth of virtual channels, and (iv) switching technique. The paper discusses in detail the architecture and characterization of the various NoC components. The paper presents results obtained by application of the model towards design space exploration, and power versus performance trade-off analysis of 4×4 mesh based NoC architecture.
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U2 - 10.1109/DATE.2004.1269067
DO - 10.1109/DATE.2004.1269067
M3 - Conference contribution
AN - SCOPUS:3042565282
SN - 0769520855
SN - 9780769520858
T3 - Proceedings - Design, Automation and Test in Europe Conference and Exhibition
SP - 1250
EP - 1255
BT - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
A2 - Gielen, G.
A2 - Figueras, J.
T2 - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
Y2 - 16 February 2004 through 20 February 2004
ER -