A power and performance model for network-on-chip architectures

Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

133 Citations (Scopus)

Abstract

Networks-on-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Innovative system-level performance models are required for designing NoC based architectures. This paper presents a VHDL based cycle accurate register transfer level model for evaluating the latency, throughput, dynamic, and leakage power consumption of NoC based interconnection architectures. We implemented a parameterized register transfer level design of the NoC architecture elements. The design is parameterized on (i) size of packets, (ii) length and width of physical links, (Hi) number, and depth of virtual channels, and (iv) switching technique. The paper discusses in detail the architecture and characterization of the various NoC components. The paper presents results obtained by application of the model towards design space exploration, and power versus performance trade-off analysis of 4×4 mesh based NoC architecture.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition
EditorsG. Gielen, J. Figueras
Pages1250-1255
Number of pages6
Volume2
DOIs
StatePublished - 2004
EventProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 - Paris, France
Duration: Feb 16 2004Feb 20 2004

Other

OtherProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
CountryFrance
CityParis
Period2/16/042/20/04

Fingerprint

Computer hardware description languages
Network-on-chip
Electric power utilization
Throughput

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Banerjee, N., Vellanki, P., & Chatha, K. S. (2004). A power and performance model for network-on-chip architectures. In G. Gielen, & J. Figueras (Eds.), Proceedings - Design, Automation and Test in Europe Conference and Exhibition (Vol. 2, pp. 1250-1255) https://doi.org/10.1109/DATE.2004.1269067

A power and performance model for network-on-chip architectures. / Banerjee, Nilanjan; Vellanki, Praveen; Chatha, Karam S.

Proceedings - Design, Automation and Test in Europe Conference and Exhibition. ed. / G. Gielen; J. Figueras. Vol. 2 2004. p. 1250-1255.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Banerjee, N, Vellanki, P & Chatha, KS 2004, A power and performance model for network-on-chip architectures. in G Gielen & J Figueras (eds), Proceedings - Design, Automation and Test in Europe Conference and Exhibition. vol. 2, pp. 1250-1255, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, Paris, France, 2/16/04. https://doi.org/10.1109/DATE.2004.1269067
Banerjee N, Vellanki P, Chatha KS. A power and performance model for network-on-chip architectures. In Gielen G, Figueras J, editors, Proceedings - Design, Automation and Test in Europe Conference and Exhibition. Vol. 2. 2004. p. 1250-1255 https://doi.org/10.1109/DATE.2004.1269067
Banerjee, Nilanjan ; Vellanki, Praveen ; Chatha, Karam S. / A power and performance model for network-on-chip architectures. Proceedings - Design, Automation and Test in Europe Conference and Exhibition. editor / G. Gielen ; J. Figueras. Vol. 2 2004. pp. 1250-1255
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