A performance model and code overlay generator for scratchpad enhanced embedded processors

Michael A. Baker, Amrit Panda, Nikhil Ghadge, Aniruddha Kadne, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

Software managed scratchpad memories (SPMs) provide improved performance and power in embedded processors by reducing required hardware resources. Performance depends strongly on the scheme used to map code and data onto the SPM, but generating optimal mappings can be extremely difficult. Here we address instruction mapping on SPMs and present a performance model and algorithm, "Code Overlay Generator" (COG), for producing high performance dynamic SPM code mappings. Our heuristic does not require profiling information, and is suitable for generating mapping solutions for large programs which are otherwise infeasible using previously proposed Integer Linear Programming (ILP) techniques. We compare our algorithm with a published heuristic and the code overlay mapping algorithm provided with the Cell Broadband Engine (CBE) Synergistic Processing Unit (SPU) compiler from IBM, spu-gcc. We find an average performance advantage of 34% compared to the previous algorithm, and 87% with respect to spugcc. We additionally show that our performance model enables improved tools for offline evaluation of code overlay performance and mapping selection.

Original languageEnglish (US)
Title of host publicationEmbedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'10
Pages287-296
Number of pages10
DOIs
StatePublished - Dec 1 2010
Event6th Embedded Systems Week, ESWEEK 2010 - 8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS'10 - Scottsdale, AZ, United States
Duration: Oct 24 2010Oct 29 2010

Publication series

NameEmbedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010

Other

Other6th Embedded Systems Week, ESWEEK 2010 - 8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS'10
CountryUnited States
CityScottsdale, AZ
Period10/24/1010/29/10

Keywords

  • Cell broadband engine
  • Code mapping
  • Code overlay
  • Compiler
  • Embedded systems
  • Scratchpad memory

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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  • Cite this

    Baker, M. A., Panda, A., Ghadge, N., Kadne, A., & Chatha, K. S. (2010). A performance model and code overlay generator for scratchpad enhanced embedded processors. In Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'10 (pp. 287-296). (Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010). https://doi.org/10.1145/1878961.1879011