TY - GEN
T1 - A performance-driven I/O pin routing algorithm
AU - Wang, Dongsheng
AU - Zhang, Ping
AU - Cheng, Chung Kuan
AU - Sen, Arunabha
N1 - Funding Information:
We would like to thank Alina Deutsch for her very helpful comments on this paper. This work was supported in part by grants from the NSF project MIP-9529077 and the California MICRO Program.
Publisher Copyright:
© 1999 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.
PY - 1999
Y1 - 1999
N2 - This paper presents a performance-driven I/O pin routing algorithm with special consideration of wire uniformity. First, a topological routing based on min-cost max-flow algorithm is proposed. In this phase, an exponential weight function is used to guide the flow distribution which is very helpful in distributing wires, globally and uniformly, on the whole routing area. Then a physical routing phase is applied to implement one-to-one connection between chip pads and I/O pins, which focuses on the wire uniformity of the fanout area nearby the periphery of chip pads. Finally, a balanced position based wire polishing approach is proposed to further improve the local wire uniformity which tries to modify each wire into a smooth curve instead of broken line while satisfying the specified design rules such as wire-wire pitch and wire-pin pitch. A routing cost function is adequately defined to guide the whole routing process, which leads to a good tradeoff between wire uniformity and wire length. The algorithm has been implemented and tested on up to 10-ring 600-pin PGA and the experimental results are very promising.
AB - This paper presents a performance-driven I/O pin routing algorithm with special consideration of wire uniformity. First, a topological routing based on min-cost max-flow algorithm is proposed. In this phase, an exponential weight function is used to guide the flow distribution which is very helpful in distributing wires, globally and uniformly, on the whole routing area. Then a physical routing phase is applied to implement one-to-one connection between chip pads and I/O pins, which focuses on the wire uniformity of the fanout area nearby the periphery of chip pads. Finally, a balanced position based wire polishing approach is proposed to further improve the local wire uniformity which tries to modify each wire into a smooth curve instead of broken line while satisfying the specified design rules such as wire-wire pitch and wire-pin pitch. A routing cost function is adequately defined to guide the whole routing process, which leads to a good tradeoff between wire uniformity and wire length. The algorithm has been implemented and tested on up to 10-ring 600-pin PGA and the experimental results are very promising.
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U2 - 10.1109/ASPDAC.1999.759779
DO - 10.1109/ASPDAC.1999.759779
M3 - Conference contribution
AN - SCOPUS:85027145929
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 129
EP - 132
BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999
Y2 - 18 January 1999 through 21 January 1999
ER -