Abstract
There has been an ever increasing demand for fast and power efficient solutions for mobile multimedia computing applications. The research discussed in this paper proposes an automated tool-set to design a reconfigurable architecture targeted towards multimedia applications, which are both data and control intensive. One important design step is custom memory design. This paper discusses a novel methodology to design a power, area and time efficient memory architecture for a given Control Data Flow Graph (CDFG) of an application. It uses the concept of Predicated Data Flow Analysis to get the memory requirements of each control path of the CDFG and a novel algorithm is used to merge these requirements. Final memory architecture is reconfigurable during run-time and a dynamic memory manager has been designed to support the same. An illustrative example involving a self-generated CDFG is shown to demonstrate the flow of the proposed algorithm. Results for various multimedia algorithms found in MPEG-4 codec show the effectiveness of this approach over memory design based on conventional Data Flow Analysis techniques. 2005 SPIE and IS&T.
| Original language | English (US) |
|---|---|
| Article number | 09 |
| Pages (from-to) | 64-71 |
| Number of pages | 8 |
| Journal | Proceedings of SPIE - The International Society for Optical Engineering |
| Volume | 5683 |
| DOIs | |
| State | Published - 2005 |
| Event | Proceedings of SPIE-IS and T Electronic Imaging - Embedded Processors for Multimedia and Communications II - San Jose, CA, United States Duration: Jan 17 2005 → Jan 18 2005 |
Keywords
- Memory Design
- Multimedia computing
- Predicated Data Flow Analysis
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Computer Science Applications
- Applied Mathematics
- Electrical and Electronic Engineering