A novel mechanism to dynamically switch speed and accuracy in systemc based transaction level models

OSCI's TLM-2.0 standard enables the simulation of functionality and timing of a system by defining two coding styles namely Loosely-timed (LT) and approximately timed (AT). Without dynamic switching between the two modes, a user interested in performance analysis is forced to execute the model in AT mode for the entire duration of simulation. A run-time switching mechanism enables user to execute uninteresting simulation portions (e.g. operating system boot) in the high speed LT mode and switch to detailed AT model only when one needs to carry out detailed microarchitectural analysis (e.g. benchmark execution). In this paper, we introduce a comprehensive switching mechanism that addresses all the potential issues during LT-to-AT and AT-to-LT transitions. We test this switching methodology on one Intel proprietary Interconnect Bus model and demonstrate a ∼24X speedup over ATonly simulations.