A novel mechanism to dynamically switch speed and accuracy in systemc based transaction level models

Zhu Zhou, Dharmin Parikh, Pradnyesh Gudadhe, Arunabha Sen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

OSCI's TLM-2.0 standard enables the simulation of functionality and timing of a system by defining two coding styles namely Loosely-timed (LT) and approximately timed (AT). Without dynamic switching between the two modes, a user interested in performance analysis is forced to execute the model in AT mode for the entire duration of simulation. A run-time switching mechanism enables user to execute uninteresting simulation portions (e.g. operating system boot) in the high speed LT mode and switch to detailed AT model only when one needs to carry out detailed microarchitectural analysis (e.g. benchmark execution). In this paper, we introduce a comprehensive switching mechanism that addresses all the potential issues during LT-to-AT and AT-to-LT transitions. We test this switching methodology on one Intel proprietary Interconnect Bus model and demonstrate a ∼24X speedup over ATonly simulations.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2009 - Proceedings of the 2009 Great Lakes Symposium on VLSI
Pages405-408
Number of pages4
DOIs
StatePublished - Nov 6 2009
Event19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09 - Boston, MA, United States
Duration: May 10 2009May 12 2009

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09
CountryUnited States
CityBoston, MA
Period5/10/095/12/09

Keywords

  • Architectural analysis
  • Dynamic switching
  • Functional modeling
  • Performance modeling
  • Simulation infrastructure

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Zhou, Z., Parikh, D., Gudadhe, P., & Sen, A. (2009). A novel mechanism to dynamically switch speed and accuracy in systemc based transaction level models. In GLSVLSI 2009 - Proceedings of the 2009 Great Lakes Symposium on VLSI (pp. 405-408). (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI). https://doi.org/10.1145/1531542.1531634