A novel hybrid radix-3/Radix-2 SAR ADC with fast convergence and low hardware complexity

This brief presents a fast-converging hybrid successive approximation register (SAR) analog-to-digital converter (ADC) based on the radix-3 and radix-2 search approaches. The radix-3 approach achieves 1.6 bits/cycle, and the radix-2 approach mitigates the effect of comparator offset and improves the accuracy of the ADC. Incorporating clock gating of comparators and efficient switching of capacitors, the proposed hybrid ADC demonstrates promising balance between hardware complexity and speed and can achieve equivalent signal-to-noise-and-distortion-ratio (SNDR) with less capacitors compared with radix-3 SAR ADC. Behavioral simulation-based results verify operation and merit of the proposed architecture. An 11-bit 45-MS/s prototype with 5% capacitor mismatch in 180-nm CMOS was simulated in SPICE and achieves 67 dB of SNDR after calibration.