Abstract

In this work, a zero-leakage nonvolatile flip-flop architecture based on a differential CMOS sense-amplifier flip-flop is presented. The flip-flop stores data in complimentarily programmed resistive memory devices during inactive period while power supply is turned off and then restores the data to flip-flop outputs once power supply is turned back on. The resistive memory technology considered here are known as programmable metallization cell (PMC) that switches via metal ion transport within a solid electrolyte. Simulations of the proposed circuit using a PMC compact model fitted to experimental data are performed to estimate the reliability of the read operation and energy consumption for both nominal and sub-threshold power supply regimes. Energy and reliability tradeoffs in the choice of the programmable low resistance state are also discussed. The proposed sense amplifier-based design is more compact than previously reported master-slave latch based nonvolatile designs and presents a modified data restore circuit for more robust read operation at subthreshold voltage supply levels. The wide margin between high and low resistance states of the PMC devices further improves robustness of the flip-flop. Lastly, possible extension of this architecture for low power logic computation application is briefly discussed.

Original languageEnglish (US)
Article number7113919
Pages (from-to)205-213
Number of pages9
JournalIEEE Journal on Emerging and Selected Topics in Circuits and Systems
Volume5
Issue number2
DOIs
StatePublished - Jun 1 2015

Keywords

  • Low power design
  • memory
  • programmable metallization cell (PMC)
  • resistive memory
  • sense amplifier

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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