A new short circuit power model for complex CMOS gates

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

In this paper we propose a new model for short circuit power estimation of CMOS gates. The short circuit power of a CMOS gate is estimated by converting the gate into an equivalent CMOS inverter and all input signal waveforms into a single equivalent input signal for the inverter. The channel width and the input to the equivalent inverter are functions of the waveforms of all the inputs. This is different from the traditional approaches where only worst case situations are considered. HSPICE simulation of NAND gates using a commercial 0.25 μm CMOS process shows that the proposed new short circuit power model for CMOS gates is much more accurate than previously reported models.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Alessandro Volta Memorial Workshop on Low-Power Design, VOLTA 1999
EditorsVincenzo Piuri
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages98-106
Number of pages9
ISBN (Electronic)0769500196, 9780769500195
DOIs
StatePublished - 1999
Event1999 IEEE Alessandro Volta Memorial Workshop on Low-Power Design, VOLTA 1999 - Como, Italy
Duration: Mar 4 1999Mar 5 1999

Publication series

NameProceedings - IEEE Alessandro Volta Memorial Workshop on Low-Power Design, VOLTA 1999

Other

Other1999 IEEE Alessandro Volta Memorial Workshop on Low-Power Design, VOLTA 1999
Country/TerritoryItaly
CityComo
Period3/4/993/5/99

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'A new short circuit power model for complex CMOS gates'. Together they form a unique fingerprint.

Cite this