A new register allocation scheme for low-power data format converters

Kala Srivatsan, Chaitali Chakrabarti, Lori E. Lucke

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

In many applications, such as digital signal processing, data format converters (DFC) are used to reformat the data transferred between processing modules. Various methods have been proposed to synthesize DFC architectures while optimizing the number of registers used to store the data. In this brief, we present a new register allocation scheme which not only minimizes the number of registers, but also minimizes the power consumption in the DFC. Low-power DFC's are synthesized by minimizing the transitions and interconnections between the registers used to store the data. We present both a heuristic and an integer linear programming formulation to solve the allocation problem. Our method shows significant improvement over previous techniques.

Original languageEnglish (US)
Pages (from-to)1250-1253
Number of pages4
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume46
Issue number9
DOIs
StatePublished - Sep 1999

Fingerprint

Digital signal processing
Linear programming
Electric power utilization
Processing

Keywords

  • Data format converters, ilp, low power

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing

Cite this

A new register allocation scheme for low-power data format converters. / Srivatsan, Kala; Chakrabarti, Chaitali; Lucke, Lori E.

In: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 46, No. 9, 09.1999, p. 1250-1253.

Research output: Contribution to journalArticle

@article{3dcbfeca9c934f239fbd2c21fd05fcfc,
title = "A new register allocation scheme for low-power data format converters",
abstract = "In many applications, such as digital signal processing, data format converters (DFC) are used to reformat the data transferred between processing modules. Various methods have been proposed to synthesize DFC architectures while optimizing the number of registers used to store the data. In this brief, we present a new register allocation scheme which not only minimizes the number of registers, but also minimizes the power consumption in the DFC. Low-power DFC's are synthesized by minimizing the transitions and interconnections between the registers used to store the data. We present both a heuristic and an integer linear programming formulation to solve the allocation problem. Our method shows significant improvement over previous techniques.",
keywords = "Data format converters, ilp, low power",
author = "Kala Srivatsan and Chaitali Chakrabarti and Lucke, {Lori E.}",
year = "1999",
month = "9",
doi = "10.1109/82.793717",
language = "English (US)",
volume = "46",
pages = "1250--1253",
journal = "IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing",
issn = "1549-7747",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "9",

}

TY - JOUR

T1 - A new register allocation scheme for low-power data format converters

AU - Srivatsan, Kala

AU - Chakrabarti, Chaitali

AU - Lucke, Lori E.

PY - 1999/9

Y1 - 1999/9

N2 - In many applications, such as digital signal processing, data format converters (DFC) are used to reformat the data transferred between processing modules. Various methods have been proposed to synthesize DFC architectures while optimizing the number of registers used to store the data. In this brief, we present a new register allocation scheme which not only minimizes the number of registers, but also minimizes the power consumption in the DFC. Low-power DFC's are synthesized by minimizing the transitions and interconnections between the registers used to store the data. We present both a heuristic and an integer linear programming formulation to solve the allocation problem. Our method shows significant improvement over previous techniques.

AB - In many applications, such as digital signal processing, data format converters (DFC) are used to reformat the data transferred between processing modules. Various methods have been proposed to synthesize DFC architectures while optimizing the number of registers used to store the data. In this brief, we present a new register allocation scheme which not only minimizes the number of registers, but also minimizes the power consumption in the DFC. Low-power DFC's are synthesized by minimizing the transitions and interconnections between the registers used to store the data. We present both a heuristic and an integer linear programming formulation to solve the allocation problem. Our method shows significant improvement over previous techniques.

KW - Data format converters, ilp, low power

UR - http://www.scopus.com/inward/record.url?scp=0033189219&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033189219&partnerID=8YFLogxK

U2 - 10.1109/82.793717

DO - 10.1109/82.793717

M3 - Article

VL - 46

SP - 1250

EP - 1253

JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

SN - 1549-7747

IS - 9

ER -