A new register allocation scheme for low-power data format converters

Kala Srivatsan, Chaitali Chakrabarti, Lori E. Lucke

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


In many applications, such as digital signal processing, data format converters (DFC) are used to reformat the data transferred between processing modules. Various methods have been proposed to synthesize DFC architectures while optimizing the number of registers used to store the data. In this brief, we present a new register allocation scheme which not only minimizes the number of registers, but also minimizes the power consumption in the DFC. Low-power DFC's are synthesized by minimizing the transitions and interconnections between the registers used to store the data. We present both a heuristic and an integer linear programming formulation to solve the allocation problem. Our method shows significant improvement over previous techniques.

Original languageEnglish (US)
Pages (from-to)1250-1253
Number of pages4
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Issue number9
StatePublished - Sep 1999


  • Data format converters, ilp, low power

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering


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