A new high-speed memory interconnect architecture using microwave interconnects and multicarrier signaling

Brahim Bensalem, James Aberle

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We present details of our proposal as well as the results of simulations and experiments, which demonstrate the merits of this approach. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW is sufficient to transmit the 64 DDR bits. The overall aggregated bus data rate achieves 240 GB data transfer with the error vector magnitude not exceeding 2.26% and phase error of 1.07 degrees or less.

Original languageEnglish (US)
Article number6624126
Pages (from-to)332-340
Number of pages9
JournalIEEE Transactions on Components, Packaging and Manufacturing Technology
Volume4
Issue number2
DOIs
StatePublished - Feb 2014

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Microwaves
Data storage equipment
Substrate integrated waveguides
Frequency division multiplexing
Microwave links
Memory architecture
Quadrature amplitude modulation
Data transfer
Experiments

Keywords

  • Double data rate memory
  • memory wall
  • signal integrity
  • substrate integrated waveguide

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Industrial and Manufacturing Engineering

Cite this

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abstract = "A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We present details of our proposal as well as the results of simulations and experiments, which demonstrate the merits of this approach. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW is sufficient to transmit the 64 DDR bits. The overall aggregated bus data rate achieves 240 GB data transfer with the error vector magnitude not exceeding 2.26{\%} and phase error of 1.07 degrees or less.",
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