A new fabric of reconfigurable fft processor for high-speed and low-cost system

Huan Liu, Wei Pan, Shui Sheng Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

A high-speed reconfigurable FFT architecture based on FPGA is proposed in this paper. The system can be configured as 32, 64,128, 256, 512 and 1024-point FFT using simplified method to control. It has been synthesized in Xilinx Virtex2p FPGA and post-simulated. Compared with Xilinx FFT IP Core with the same function ,this FFT fabric proposed has saved almost 8%-9% (equivalent gates) in resources consumption while increased nearly 6%-25% in clock frequency and decreased 56-116 cycles of delays from first input data to the first result data, indicating high computing efficiency. On the other hand, power consumption is also slightly fewer than the IP Core's. The fabric we presented in this paper is suitable for use in digital signal process with high-speed and low-cost.

Original languageEnglish (US)
Title of host publicationProceedings of the 7th International Conference on Machine Learning and Cybernetics, ICMLC
Pages3525-3529
Number of pages5
Volume6
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event7th International Conference on Machine Learning and Cybernetics, ICMLC - Kunming, China
Duration: Jul 12 2008Jul 15 2008

Other

Other7th International Conference on Machine Learning and Cybernetics, ICMLC
CountryChina
CityKunming
Period7/12/087/15/08

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Keywords

  • FFT
  • FPGA
  • Reconfigurable

ASJC Scopus subject areas

  • Artificial Intelligence
  • Human-Computer Interaction
  • Control and Systems Engineering

Cite this

Liu, H., Pan, W., & Lin, S. S. (2008). A new fabric of reconfigurable fft processor for high-speed and low-cost system. In Proceedings of the 7th International Conference on Machine Learning and Cybernetics, ICMLC (Vol. 6, pp. 3525-3529). [4621014] https://doi.org/10.1109/ICMLC.2008.4621014