A new architecture for the viterbi decoder for code rate k/n

Hsiang Ling Li, Chaitali Chakrabarti

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

A novel VLSI architecture is proposed for implementing a long constraint length Viterbi decoder IVU) for code rate k/n. This architecture is based on the encoding structure where k input bits are shifted into fc shift registers in each cycle. The architecture is designed in a hierarchical manner by breaking the system into several levels and designing each level independently. The tasks in the design of each level range from determining the number of computation units and the interconnection between the units to the allocation and scheduling of operations. Additional design issues such as in-place storage of accumulated path metrics and trace back implementation of the survivor memory have also been addressed. The resulting architecture is regular has a foldable global topology and is very flexible. It also achieves a better than linear trade-off between hardware complexity and computation time.

Original languageEnglish (US)
Pages (from-to)158-164
Number of pages7
JournalIEEE Transactions on Communications
Volume44
Issue number2
DOIs
Publication statusPublished - 1996

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Networks and Communications

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