A new analytical delay and noise model for on-chip RLC interconnect

Yu Cao; X. Huang; D. Sylvester; N. Chang; C. Hu

A new analytical delay and noise model for on-chip RLC interconnect

Yu Cao, X. Huang, D. Sylvester, N. Chang, C. Hu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we develop a 2 ^nd order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1 ^st order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.

Original language	English (US)
Title of host publication	Technical Digest - International Electron Devices Meeting
Pages	823-826
Number of pages	4
State	Published - 2000
Externally published	Yes
Event	2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States Duration: Dec 10 2000 → Dec 13 2000

Other

Other	2000 IEEE International Electron Devices Meeting
Country/Territory	United States
City	San Francisco, CA
Period	12/10/00 → 12/13/00

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "A new analytical delay and noise model for on-chip RLC interconnect",

abstract = "In this paper, we develop a 2 nd order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1 st order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters. ",

author = "Yu Cao and X. Huang and D. Sylvester and N. Chang and C. Hu",

year = "2000",

language = "English (US)",

pages = "823--826",

booktitle = "Technical Digest - International Electron Devices Meeting",

note = "2000 IEEE International Electron Devices Meeting ; Conference date: 10-12-2000 Through 13-12-2000",

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TY - GEN

T1 - A new analytical delay and noise model for on-chip RLC interconnect

AU - Cao, Yu

AU - Huang, X.

AU - Sylvester, D.

AU - Chang, N.

AU - Hu, C.

PY - 2000

Y1 - 2000

N2 - In this paper, we develop a 2 nd order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1 st order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.

AB - In this paper, we develop a 2 nd order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1 st order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.

UR - http://www.scopus.com/inward/record.url?scp=0034449490&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034449490&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0034449490

SP - 823

EP - 826

BT - Technical Digest - International Electron Devices Meeting

T2 - 2000 IEEE International Electron Devices Meeting

Y2 - 10 December 2000 through 13 December 2000

ER -

A new analytical delay and noise model for on-chip RLC interconnect

Abstract

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ASJC Scopus subject areas

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