A new analytical delay and noise model for on-chip RLC interconnect

Yu Cao, X. Huang, D. Sylvester, N. Chang, C. Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

In this paper, we develop a 2 nd order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1 st order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.

Original languageEnglish (US)
Title of host publicationTechnical Digest - International Electron Devices Meeting
Pages823-826
Number of pages4
Publication statusPublished - 2000
Externally publishedYes
Event2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
Duration: Dec 10 2000Dec 13 2000

Other

Other2000 IEEE International Electron Devices Meeting
CountryUnited States
CitySan Francisco, CA
Period12/10/0012/13/00

    Fingerprint

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Cao, Y., Huang, X., Sylvester, D., Chang, N., & Hu, C. (2000). A new analytical delay and noise model for on-chip RLC interconnect. In Technical Digest - International Electron Devices Meeting (pp. 823-826)