A multi-bit binary arithmetic coding technique

K. Andra, T. Acharya, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

In this paper, we propose a new methodology for binary arithmetic coding which reduces the number of arithmetic operations significantly at the expense of a mild reduction in compression ratio. We achieve this by (i) considering a two symbol non-overlapping window and not coding the second symbol if both of them are Most Probable Symbols and (ii) moving the majority of computations to the Least Probable Symbol path. As a result, we reduce the additions/substractions required by 60-70%, with a loss of compression ratio of about 1-3% 3% compared to the Q-coder. This reduction in computational complexity makes the proposed technique particularly suitable for low-power VLSI implementation. In this paper, we have described the proposed algorithm and analyzed the results. We have also described a VLSI architecture capable of carrying out the algorithm.

Original languageEnglish (US)
Title of host publicationIEEE International Conference on Image Processing
Pages928-931
Number of pages4
Volume1
StatePublished - 2000
EventInternational Conference on Image Processing (ICIP 2000) - Vancouver, BC, Canada
Duration: Sep 10 2000Sep 13 2000

Other

OtherInternational Conference on Image Processing (ICIP 2000)
CountryCanada
CityVancouver, BC
Period9/10/009/13/00

ASJC Scopus subject areas

  • Computer Vision and Pattern Recognition
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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