A methodology to improve timing yield in the presence of process variations

Sreeja Raj, Sarma B K Vrudhula, Janet Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

53 Scopus citations

Abstract

The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing uncertainty in the performance of CMOS circuits. Accounting for the worst case values of all parameters will result in an unacceptably low timing yield. Design for Variability, which involves designing to achieve a given level of confidence in the performance of ICs, is fast becoming an indispensable part of IC design methodology. This paper 1 describes a method to identify certain paths in the circuit that are responsible for the spread of timing performance. The method is based on defining a disutility function of the gate and path delays, which includes both the means and variances of the delay random variables. Based on the moments of this disutility function, an algorithm is presented which selects a subset of paths (called undominated paths) as being most responsible for the variation in timing performance. Next, a statistical gate sizing algorithm is presented, which is aimed at minimizing the delay variability of the nodes in the selected paths subject to constraints on the critical path delay and the area penalty. Monte-Carlo simulations with ISCAS '85 benchmark circuits show that our statistical optimization approach results in significant improvements in timing yield over traditional deterministic sizing methods.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages448-453
Number of pages6
StatePublished - 2004
Externally publishedYes
EventProceedings of the 41st Design Automation Conference - San Diego, CA, United States
Duration: Jun 7 2004Jun 11 2004

Other

OtherProceedings of the 41st Design Automation Conference
CountryUnited States
CitySan Diego, CA
Period6/7/046/11/04

Keywords

  • Gate Sizing
  • Timing Analysis
  • Timing Yield

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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