TY - GEN
T1 - A methodology to improve linearity of analog RRAM for neuromorphic computing
AU - Wu, Wei
AU - Wu, Huaqiang
AU - Gao, Bin
AU - Yao, Peng
AU - Zhang, Xiang
AU - Peng, Xiaochen
AU - Yu, Shimeng
AU - Qian, He
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/10/25
Y1 - 2018/10/25
N2 - The conductance tuning linearity is an important parameter of analog RRAM for neuromorphic computing. This work presents a novel methodology to improve the conductance tuning linearity of the filamentary RRAM. An electro-thermal modulation layer is designed and introduced to control the distribution of electric field and temperature in the filament region. For the first time, a HfOx based RRAM is demonstrated with linear analog SET, linear analog RESET, 50ns speed, 10× analog tuning window, 100kω on-state resistance, and high temperature retention for multilevel states. The excellent performances of the analog RRAM devices enable high accuracy online learning in a neural network.
AB - The conductance tuning linearity is an important parameter of analog RRAM for neuromorphic computing. This work presents a novel methodology to improve the conductance tuning linearity of the filamentary RRAM. An electro-thermal modulation layer is designed and introduced to control the distribution of electric field and temperature in the filament region. For the first time, a HfOx based RRAM is demonstrated with linear analog SET, linear analog RESET, 50ns speed, 10× analog tuning window, 100kω on-state resistance, and high temperature retention for multilevel states. The excellent performances of the analog RRAM devices enable high accuracy online learning in a neural network.
KW - Analog RRAM
KW - Online learning
KW - Synapse
UR - http://www.scopus.com/inward/record.url?scp=85056849709&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85056849709&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2018.8510690
DO - 10.1109/VLSIT.2018.8510690
M3 - Conference contribution
AN - SCOPUS:85056849709
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 103
EP - 104
BT - 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Y2 - 18 June 2018 through 22 June 2018
ER -