A methodology to improve linearity of analog RRAM for neuromorphic computing

Wei Wu, Huaqiang Wu, Bin Gao, Peng Yao, Xiang Zhang, Xiaochen Peng, Shimeng Yu, He Qian

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

The conductance tuning linearity is an important parameter of analog RRAM for neuromorphic computing. This work presents a novel methodology to improve the conductance tuning linearity of the filamentary RRAM. An electro-thermal modulation layer is designed and introduced to control the distribution of electric field and temperature in the filament region. For the first time, a HfOx based RRAM is demonstrated with linear analog SET, linear analog RESET, 50ns speed, 10× analog tuning window, 100kω on-state resistance, and high temperature retention for multilevel states. The excellent performances of the analog RRAM devices enable high accuracy online learning in a neural network.

Original languageEnglish (US)
Title of host publication2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages103-104
Number of pages2
Volume2018-June
ISBN (Electronic)9781538642160
DOIs
StatePublished - Oct 25 2018
Event38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States
Duration: Jun 18 2018Jun 22 2018

Other

Other38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
CountryUnited States
CityHonolulu
Period6/18/186/22/18

Fingerprint

Tuning
Electric fields
Modulation
Neural networks
Temperature
RRAM
Hot Temperature

Keywords

  • Analog RRAM
  • Online learning
  • Synapse

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Wu, W., Wu, H., Gao, B., Yao, P., Zhang, X., Peng, X., ... Qian, H. (2018). A methodology to improve linearity of analog RRAM for neuromorphic computing. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (Vol. 2018-June, pp. 103-104). [8510690] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510690

A methodology to improve linearity of analog RRAM for neuromorphic computing. / Wu, Wei; Wu, Huaqiang; Gao, Bin; Yao, Peng; Zhang, Xiang; Peng, Xiaochen; Yu, Shimeng; Qian, He.

2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Vol. 2018-June Institute of Electrical and Electronics Engineers Inc., 2018. p. 103-104 8510690.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wu, W, Wu, H, Gao, B, Yao, P, Zhang, X, Peng, X, Yu, S & Qian, H 2018, A methodology to improve linearity of analog RRAM for neuromorphic computing. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. vol. 2018-June, 8510690, Institute of Electrical and Electronics Engineers Inc., pp. 103-104, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 6/18/18. https://doi.org/10.1109/VLSIT.2018.8510690
Wu W, Wu H, Gao B, Yao P, Zhang X, Peng X et al. A methodology to improve linearity of analog RRAM for neuromorphic computing. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Vol. 2018-June. Institute of Electrical and Electronics Engineers Inc. 2018. p. 103-104. 8510690 https://doi.org/10.1109/VLSIT.2018.8510690
Wu, Wei ; Wu, Huaqiang ; Gao, Bin ; Yao, Peng ; Zhang, Xiang ; Peng, Xiaochen ; Yu, Shimeng ; Qian, He. / A methodology to improve linearity of analog RRAM for neuromorphic computing. 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Vol. 2018-June Institute of Electrical and Electronics Engineers Inc., 2018. pp. 103-104
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