TY - GEN
T1 - A methodology for layout aware design and optimization of custom network-on-chip architectures
AU - Srinivasan, Krishnan
AU - Chatha, Karam S.
PY - 2006
Y1 - 2006
N2 - Network-on-chip (NoC) has been proposed as a solution for the interconnection architecture design problem of system-on-chip (SoC) design in nanoscale Technologies. NoC architecture for application specific SoC can be optimized by constructing custom topologies that are more suitable for the given application. In nanoscale Technologies, the link energy consumption constitute a considerable part of the total communication energy. Therefore, the total energy consumption of the NoC is strongly influenced by system-level floorplan. In this paper, we present a novel integer linear programming (ILP) based technique for joint optimization of NoC with system-level floorplan. We also present a clustering based heuristic technique to reduce the runtime of the ILP formulation. Experimental results with realistic benchmarks applications demonstrate superiority of custom NoC topologies generated by our techniques over mesh based networks, and high quality of the clustering based technique when compared with the ILP formulation.
AB - Network-on-chip (NoC) has been proposed as a solution for the interconnection architecture design problem of system-on-chip (SoC) design in nanoscale Technologies. NoC architecture for application specific SoC can be optimized by constructing custom topologies that are more suitable for the given application. In nanoscale Technologies, the link energy consumption constitute a considerable part of the total communication energy. Therefore, the total energy consumption of the NoC is strongly influenced by system-level floorplan. In this paper, we present a novel integer linear programming (ILP) based technique for joint optimization of NoC with system-level floorplan. We also present a clustering based heuristic technique to reduce the runtime of the ILP formulation. Experimental results with realistic benchmarks applications demonstrate superiority of custom NoC topologies generated by our techniques over mesh based networks, and high quality of the clustering based technique when compared with the ILP formulation.
UR - http://www.scopus.com/inward/record.url?scp=49749095189&partnerID=8YFLogxK
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U2 - 10.1109/ISQED.2006.13
DO - 10.1109/ISQED.2006.13
M3 - Conference contribution
AN - SCOPUS:49749095189
SN - 0769525237
SN - 9780769525235
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 352
EP - 357
BT - Proceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006
T2 - 7th International Symposium on Quality Electronic Design, ISQED 2006
Y2 - 27 March 2006 through 29 March 2006
ER -