A methodology for layout aware design and optimization of custom network-on-chip architectures

Krishnan Srinivasan, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

Network-on-chip (NoC) has been proposed as a solution for the interconnection architecture design problem of system-on-chip (SoC) design in nanoscale Technologies. NoC architecture for application specific SoC can be optimized by constructing custom topologies that are more suitable for the given application. In nanoscale Technologies, the link energy consumption constitute a considerable part of the total communication energy. Therefore, the total energy consumption of the NoC is strongly influenced by system-level floorplan. In this paper, we present a novel integer linear programming (ILP) based technique for joint optimization of NoC with system-level floorplan. We also present a clustering based heuristic technique to reduce the runtime of the ILP formulation. Experimental results with realistic benchmarks applications demonstrate superiority of custom NoC topologies generated by our techniques over mesh based networks, and high quality of the clustering based technique when compared with the ILP formulation.

Original languageEnglish (US)
Title of host publicationProceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006
Pages352-357
Number of pages6
DOIs
StatePublished - Dec 1 2006
Event7th International Symposium on Quality Electronic Design, ISQED 2006 - San Jose, CA, United States
Duration: Mar 27 2006Mar 29 2006

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other7th International Symposium on Quality Electronic Design, ISQED 2006
CountryUnited States
CitySan Jose, CA
Period3/27/063/29/06

    Fingerprint

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Srinivasan, K., & Chatha, K. S. (2006). A methodology for layout aware design and optimization of custom network-on-chip architectures. In Proceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006 (pp. 352-357). [1613162] (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2006.13