A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity

Lawrence T. Clark, Mohammed Kabir, Jonathan E. Knudsen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A flip-flop using a combination of thin and thick gate transistors combines high performance and low standby power. Setup and hold times are controlled by the master latch implemented in high performance transistors, while a thick gate slave latch provides state retention at low standby power when the high performance circuit power supply is gated off. The design has reduced circuit and power-down control complexity compared to previously described circuits using thick gate shadow latches for low standby power state storage. Measured test chip results on a foundry 130 nm process prove the viability of the design. The thick gate shadow latches are shown to have good retention capability at low supply voltages, suggesting that reduced shadow latch supply voltage during standby will be effective at mitigating the drain to bulk leakage components that are increasingly limiting for low power standby modes.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages571-574
Number of pages4
ISBN (Print)1424407869, 9781424407866
DOIs
StatePublished - 2007
Event29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States
Duration: Sep 16 2007Sep 19 2007

Other

Other29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
CountryUnited States
CitySan Jose
Period9/16/079/19/07

Fingerprint

Flip flop circuits
Transistors
Power supply circuits
Networks (circuits)
Electric potential
Foundries

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Clark, L. T., Kabir, M., & Knudsen, J. E. (2007). A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 571-574). [4405796] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405796

A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity. / Clark, Lawrence T.; Kabir, Mohammed; Knudsen, Jonathan E.

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. p. 571-574 4405796.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clark, LT, Kabir, M & Knudsen, JE 2007, A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity. in Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007., 4405796, Institute of Electrical and Electronics Engineers Inc., pp. 571-574, 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007, San Jose, United States, 9/16/07. https://doi.org/10.1109/CICC.2007.4405796
Clark LT, Kabir M, Knudsen JE. A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc. 2007. p. 571-574. 4405796 https://doi.org/10.1109/CICC.2007.4405796
Clark, Lawrence T. ; Kabir, Mohammed ; Knudsen, Jonathan E. / A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity. Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. pp. 571-574
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