A low-power 2.5-GHz 90-nm level 1 cache and memory management unit

Jonathan R. Haigh, Michael W. Wilkerson, Jay B. Miller, Timothy S. Beatty, Stephen J. Strazdus, Lawrence T. Clark

Research output: Contribution to journalArticle

23 Citations (Scopus)

Abstract

The design of a 90-nm virtually addressed cache subsystem with separate 32-kB instruction and data caches is described. The circuits and microarchitecture are illustrated, including architecture level trace data validating low-power features and provisions to support snooping while maintaining the latency and power of virtual addressing. Low-power memory management unit design including a translation lookaside buffer with process identifier mapping is also described. Level 1 caches with support for high bandwidth, single cycle 256 bit fill and evict, as well as features for low power are also described. The design approaches are validated through both simulation and experimental results.

Original languageEnglish (US)
Pages (from-to)1190-1199
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume40
Issue number5
DOIs
StatePublished - May 2005

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Memory management units
Bandwidth
Networks (circuits)

Keywords

  • Cache memories
  • Computer architecture
  • High-speed integrated circuits
  • Low power
  • Microprocessors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Haigh, J. R., Wilkerson, M. W., Miller, J. B., Beatty, T. S., Strazdus, S. J., & Clark, L. T. (2005). A low-power 2.5-GHz 90-nm level 1 cache and memory management unit. IEEE Journal of Solid-State Circuits, 40(5), 1190-1199. https://doi.org/10.1109/JSSC.2005.845971

A low-power 2.5-GHz 90-nm level 1 cache and memory management unit. / Haigh, Jonathan R.; Wilkerson, Michael W.; Miller, Jay B.; Beatty, Timothy S.; Strazdus, Stephen J.; Clark, Lawrence T.

In: IEEE Journal of Solid-State Circuits, Vol. 40, No. 5, 05.2005, p. 1190-1199.

Research output: Contribution to journalArticle

Haigh, JR, Wilkerson, MW, Miller, JB, Beatty, TS, Strazdus, SJ & Clark, LT 2005, 'A low-power 2.5-GHz 90-nm level 1 cache and memory management unit', IEEE Journal of Solid-State Circuits, vol. 40, no. 5, pp. 1190-1199. https://doi.org/10.1109/JSSC.2005.845971
Haigh JR, Wilkerson MW, Miller JB, Beatty TS, Strazdus SJ, Clark LT. A low-power 2.5-GHz 90-nm level 1 cache and memory management unit. IEEE Journal of Solid-State Circuits. 2005 May;40(5):1190-1199. https://doi.org/10.1109/JSSC.2005.845971
Haigh, Jonathan R. ; Wilkerson, Michael W. ; Miller, Jay B. ; Beatty, Timothy S. ; Strazdus, Stephen J. ; Clark, Lawrence T. / A low-power 2.5-GHz 90-nm level 1 cache and memory management unit. In: IEEE Journal of Solid-State Circuits. 2005 ; Vol. 40, No. 5. pp. 1190-1199.
@article{85d16121fbc04537acebdb4d470124c2,
title = "A low-power 2.5-GHz 90-nm level 1 cache and memory management unit",
abstract = "The design of a 90-nm virtually addressed cache subsystem with separate 32-kB instruction and data caches is described. The circuits and microarchitecture are illustrated, including architecture level trace data validating low-power features and provisions to support snooping while maintaining the latency and power of virtual addressing. Low-power memory management unit design including a translation lookaside buffer with process identifier mapping is also described. Level 1 caches with support for high bandwidth, single cycle 256 bit fill and evict, as well as features for low power are also described. The design approaches are validated through both simulation and experimental results.",
keywords = "Cache memories, Computer architecture, High-speed integrated circuits, Low power, Microprocessors",
author = "Haigh, {Jonathan R.} and Wilkerson, {Michael W.} and Miller, {Jay B.} and Beatty, {Timothy S.} and Strazdus, {Stephen J.} and Clark, {Lawrence T.}",
year = "2005",
month = "5",
doi = "10.1109/JSSC.2005.845971",
language = "English (US)",
volume = "40",
pages = "1190--1199",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "5",

}

TY - JOUR

T1 - A low-power 2.5-GHz 90-nm level 1 cache and memory management unit

AU - Haigh, Jonathan R.

AU - Wilkerson, Michael W.

AU - Miller, Jay B.

AU - Beatty, Timothy S.

AU - Strazdus, Stephen J.

AU - Clark, Lawrence T.

PY - 2005/5

Y1 - 2005/5

N2 - The design of a 90-nm virtually addressed cache subsystem with separate 32-kB instruction and data caches is described. The circuits and microarchitecture are illustrated, including architecture level trace data validating low-power features and provisions to support snooping while maintaining the latency and power of virtual addressing. Low-power memory management unit design including a translation lookaside buffer with process identifier mapping is also described. Level 1 caches with support for high bandwidth, single cycle 256 bit fill and evict, as well as features for low power are also described. The design approaches are validated through both simulation and experimental results.

AB - The design of a 90-nm virtually addressed cache subsystem with separate 32-kB instruction and data caches is described. The circuits and microarchitecture are illustrated, including architecture level trace data validating low-power features and provisions to support snooping while maintaining the latency and power of virtual addressing. Low-power memory management unit design including a translation lookaside buffer with process identifier mapping is also described. Level 1 caches with support for high bandwidth, single cycle 256 bit fill and evict, as well as features for low power are also described. The design approaches are validated through both simulation and experimental results.

KW - Cache memories

KW - Computer architecture

KW - High-speed integrated circuits

KW - Low power

KW - Microprocessors

UR - http://www.scopus.com/inward/record.url?scp=18444419119&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=18444419119&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2005.845971

DO - 10.1109/JSSC.2005.845971

M3 - Article

AN - SCOPUS:18444419119

VL - 40

SP - 1190

EP - 1199

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 5

ER -