A low-power 2.5-GHz 90-nm level 1 cache and memory management unit

Jonathan R. Haigh, Michael W. Wilkerson, Jay B. Miller, Timothy S. Beatty, Stephen J. Strazdus, Lawrence T. Clark

Research output: Contribution to journalArticlepeer-review

23 Scopus citations

Abstract

The design of a 90-nm virtually addressed cache subsystem with separate 32-kB instruction and data caches is described. The circuits and microarchitecture are illustrated, including architecture level trace data validating low-power features and provisions to support snooping while maintaining the latency and power of virtual addressing. Low-power memory management unit design including a translation lookaside buffer with process identifier mapping is also described. Level 1 caches with support for high bandwidth, single cycle 256 bit fill and evict, as well as features for low power are also described. The design approaches are validated through both simulation and experimental results.

Original languageEnglish (US)
Pages (from-to)1190-1199
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume40
Issue number5
DOIs
StatePublished - May 1 2005

Keywords

  • Cache memories
  • Computer architecture
  • High-speed integrated circuits
  • Low power
  • Microprocessors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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