A low latency and low power indirect topology for on-chip communication

Usman Ali Gulzari, Sarzamin Khan, Muhammad Sajid, Sheraz Anjum, Frank Sill Torres, Hessam Sarjoughian, Abdullah Gani

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Abstract

This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63% and 17.36% compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by upto33.82% and 19.45%, while energy consumption can be improved byup-to32.91% and 16.83% compared to BFT and SMBFT, respectively.

Original languageEnglish (US)
Article numbere0222759
JournalPloS one
Volume14
Issue number10
DOIs
Publication statusPublished - Jan 1 2019

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ASJC Scopus subject areas

  • Biochemistry, Genetics and Molecular Biology(all)
  • Agricultural and Biological Sciences(all)
  • General

Cite this

Gulzari, U. A., Khan, S., Sajid, M., Anjum, S., Torres, F. S., Sarjoughian, H., & Gani, A. (2019). A low latency and low power indirect topology for on-chip communication. PloS one, 14(10), [e0222759]. https://doi.org/10.1371/journal.pone.0222759