A low latency and low power indirect topology for on-chip communication

Usman Ali Gulzari, Sarzamin Khan, Muhammad Sajid, Sheraz Anjum, Frank Sill Torres, Hessam Sarjoughian, Abdullah Gani

Research output: Contribution to journalArticle

Abstract

This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63% and 17.36% compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by upto33.82% and 19.45%, while energy consumption can be improved byup-to32.91% and 16.83% compared to BFT and SMBFT, respectively.

Original languageEnglish (US)
Article numbere0222759
JournalPloS one
Volume14
Issue number10
DOIs
StatePublished - Jan 1 2019

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Butterflies
butterflies
topology
Fats
Communication
Topology
lipids
Energy dissipation
Power (Psychology)
Architectural design
Workload
Routers
Energy utilization

ASJC Scopus subject areas

  • Biochemistry, Genetics and Molecular Biology(all)
  • Agricultural and Biological Sciences(all)
  • General

Cite this

Gulzari, U. A., Khan, S., Sajid, M., Anjum, S., Torres, F. S., Sarjoughian, H., & Gani, A. (2019). A low latency and low power indirect topology for on-chip communication. PloS one, 14(10), [e0222759]. https://doi.org/10.1371/journal.pone.0222759

A low latency and low power indirect topology for on-chip communication. / Gulzari, Usman Ali; Khan, Sarzamin; Sajid, Muhammad; Anjum, Sheraz; Torres, Frank Sill; Sarjoughian, Hessam; Gani, Abdullah.

In: PloS one, Vol. 14, No. 10, e0222759, 01.01.2019.

Research output: Contribution to journalArticle

Gulzari, UA, Khan, S, Sajid, M, Anjum, S, Torres, FS, Sarjoughian, H & Gani, A 2019, 'A low latency and low power indirect topology for on-chip communication', PloS one, vol. 14, no. 10, e0222759. https://doi.org/10.1371/journal.pone.0222759
Gulzari, Usman Ali ; Khan, Sarzamin ; Sajid, Muhammad ; Anjum, Sheraz ; Torres, Frank Sill ; Sarjoughian, Hessam ; Gani, Abdullah. / A low latency and low power indirect topology for on-chip communication. In: PloS one. 2019 ; Vol. 14, No. 10.
@article{445a06eea5964197a0fe685a8ef32ad6,
title = "A low latency and low power indirect topology for on-chip communication",
abstract = "This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63{\%} and 17.36{\%} compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by upto33.82{\%} and 19.45{\%}, while energy consumption can be improved byup-to32.91{\%} and 16.83{\%} compared to BFT and SMBFT, respectively.",
author = "Gulzari, {Usman Ali} and Sarzamin Khan and Muhammad Sajid and Sheraz Anjum and Torres, {Frank Sill} and Hessam Sarjoughian and Abdullah Gani",
year = "2019",
month = "1",
day = "1",
doi = "10.1371/journal.pone.0222759",
language = "English (US)",
volume = "14",
journal = "PLoS One",
issn = "1932-6203",
publisher = "Public Library of Science",
number = "10",

}

TY - JOUR

T1 - A low latency and low power indirect topology for on-chip communication

AU - Gulzari, Usman Ali

AU - Khan, Sarzamin

AU - Sajid, Muhammad

AU - Anjum, Sheraz

AU - Torres, Frank Sill

AU - Sarjoughian, Hessam

AU - Gani, Abdullah

PY - 2019/1/1

Y1 - 2019/1/1

N2 - This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63% and 17.36% compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by upto33.82% and 19.45%, while energy consumption can be improved byup-to32.91% and 16.83% compared to BFT and SMBFT, respectively.

AB - This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63% and 17.36% compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by upto33.82% and 19.45%, while energy consumption can be improved byup-to32.91% and 16.83% compared to BFT and SMBFT, respectively.

UR - http://www.scopus.com/inward/record.url?scp=85072809163&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85072809163&partnerID=8YFLogxK

U2 - 10.1371/journal.pone.0222759

DO - 10.1371/journal.pone.0222759

M3 - Article

C2 - 31577809

AN - SCOPUS:85072809163

VL - 14

JO - PLoS One

JF - PLoS One

SN - 1932-6203

IS - 10

M1 - e0222759

ER -