TY - GEN
T1 - A low complexity heuristic for design of custom network-on-chip architectures
AU - Srinivasan, Krishnan
AU - Chatha, Karam S.
PY - 2006
Y1 - 2006
N2 - Network-on-Chip (NoC) has been proposed to replace traditional bus based architectures to address the global communication challenges in nanoscale technologies. In future SoC architectures, minimizing power consumption will continue to be an important design goal. In this paper, we present a novel heuristic technique consisting of system-level physical design, and interconnection network generation that generates custom low power NoC architectures for application specific SoC. We demonstrate the quality of the solutions produced by our technique by experimentation with many benchmarks. Our technique has a low computational complexity, and consumes only 1.25 times the power consumption, and 0.85 times the number of router resources compared to an optimal MILP based technique [1] whose computational complexity is not bounded.
AB - Network-on-Chip (NoC) has been proposed to replace traditional bus based architectures to address the global communication challenges in nanoscale technologies. In future SoC architectures, minimizing power consumption will continue to be an important design goal. In this paper, we present a novel heuristic technique consisting of system-level physical design, and interconnection network generation that generates custom low power NoC architectures for application specific SoC. We demonstrate the quality of the solutions produced by our technique by experimentation with many benchmarks. Our technique has a low computational complexity, and consumes only 1.25 times the power consumption, and 0.85 times the number of router resources compared to an optimal MILP based technique [1] whose computational complexity is not bounded.
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U2 - 10.1109/date.2006.244034
DO - 10.1109/date.2006.244034
M3 - Conference contribution
AN - SCOPUS:34047167070
SN - 3981080114
SN - 9783981080117
T3 - Proceedings -Design, Automation and Test in Europe, DATE
BT - Proceedings - Design, Automation and Test in Europe, DATE'06
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Design, Automation and Test in Europe, DATE'06
Y2 - 6 March 2006 through 10 March 2006
ER -