A low complexity heuristic for design of custom network-on-chip architectures

Krishnan Srinivasan, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

61 Citations (Scopus)

Abstract

Network-on-Chip (NoC) has been proposed to replace traditional bus based architectures to address the global communication challenges in nanoscale technologies. In future SoC architectures, minimizing power consumption will continue to be an important design goal. In this paper, we present a novel heuristic technique consisting of system-level physical design, and interconnection network generation that generates custom low power NoC architectures for application specific SoC. We demonstrate the quality of the solutions produced by our technique by experimentation with many benchmarks. Our technique has a low computational complexity, and consumes only 1.25 times the power consumption, and 0.85 times the number of router resources compared to an optimal MILP based technique [1] whose computational complexity is not bounded.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
Volume1
StatePublished - 2006
EventDesign, Automation and Test in Europe, DATE'06 - Munich, Germany
Duration: Mar 6 2006Mar 10 2006

Other

OtherDesign, Automation and Test in Europe, DATE'06
CountryGermany
CityMunich
Period3/6/063/10/06

Fingerprint

Computational complexity
Electric power utilization
Routers
Communication
Network-on-chip
System-on-chip

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Srinivasan, K., & Chatha, K. S. (2006). A low complexity heuristic for design of custom network-on-chip architectures. In Proceedings -Design, Automation and Test in Europe, DATE (Vol. 1). [1656863]

A low complexity heuristic for design of custom network-on-chip architectures. / Srinivasan, Krishnan; Chatha, Karam S.

Proceedings -Design, Automation and Test in Europe, DATE. Vol. 1 2006. 1656863.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Srinivasan, K & Chatha, KS 2006, A low complexity heuristic for design of custom network-on-chip architectures. in Proceedings -Design, Automation and Test in Europe, DATE. vol. 1, 1656863, Design, Automation and Test in Europe, DATE'06, Munich, Germany, 3/6/06.
Srinivasan K, Chatha KS. A low complexity heuristic for design of custom network-on-chip architectures. In Proceedings -Design, Automation and Test in Europe, DATE. Vol. 1. 2006. 1656863
Srinivasan, Krishnan ; Chatha, Karam S. / A low complexity heuristic for design of custom network-on-chip architectures. Proceedings -Design, Automation and Test in Europe, DATE. Vol. 1 2006.
@inproceedings{6230713b5a2349189594aaea397596dc,
title = "A low complexity heuristic for design of custom network-on-chip architectures",
abstract = "Network-on-Chip (NoC) has been proposed to replace traditional bus based architectures to address the global communication challenges in nanoscale technologies. In future SoC architectures, minimizing power consumption will continue to be an important design goal. In this paper, we present a novel heuristic technique consisting of system-level physical design, and interconnection network generation that generates custom low power NoC architectures for application specific SoC. We demonstrate the quality of the solutions produced by our technique by experimentation with many benchmarks. Our technique has a low computational complexity, and consumes only 1.25 times the power consumption, and 0.85 times the number of router resources compared to an optimal MILP based technique [1] whose computational complexity is not bounded.",
author = "Krishnan Srinivasan and Chatha, {Karam S.}",
year = "2006",
language = "English (US)",
isbn = "3981080114",
volume = "1",
booktitle = "Proceedings -Design, Automation and Test in Europe, DATE",

}

TY - GEN

T1 - A low complexity heuristic for design of custom network-on-chip architectures

AU - Srinivasan, Krishnan

AU - Chatha, Karam S.

PY - 2006

Y1 - 2006

N2 - Network-on-Chip (NoC) has been proposed to replace traditional bus based architectures to address the global communication challenges in nanoscale technologies. In future SoC architectures, minimizing power consumption will continue to be an important design goal. In this paper, we present a novel heuristic technique consisting of system-level physical design, and interconnection network generation that generates custom low power NoC architectures for application specific SoC. We demonstrate the quality of the solutions produced by our technique by experimentation with many benchmarks. Our technique has a low computational complexity, and consumes only 1.25 times the power consumption, and 0.85 times the number of router resources compared to an optimal MILP based technique [1] whose computational complexity is not bounded.

AB - Network-on-Chip (NoC) has been proposed to replace traditional bus based architectures to address the global communication challenges in nanoscale technologies. In future SoC architectures, minimizing power consumption will continue to be an important design goal. In this paper, we present a novel heuristic technique consisting of system-level physical design, and interconnection network generation that generates custom low power NoC architectures for application specific SoC. We demonstrate the quality of the solutions produced by our technique by experimentation with many benchmarks. Our technique has a low computational complexity, and consumes only 1.25 times the power consumption, and 0.85 times the number of router resources compared to an optimal MILP based technique [1] whose computational complexity is not bounded.

UR - http://www.scopus.com/inward/record.url?scp=34047167070&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34047167070&partnerID=8YFLogxK

M3 - Conference contribution

SN - 3981080114

SN - 9783981080117

VL - 1

BT - Proceedings -Design, Automation and Test in Europe, DATE

ER -