TY - GEN
T1 - A low 1/f noise CMOS low-dropout regulator with current-mode feedback buffer amplifier
AU - Oh, Wonseok
AU - Bakkaloglu, Bertan
AU - Aravind, Bhaskar
AU - Hoon, Siew Kuok
PY - 2006/12/1
Y1 - 2006/12/1
N2 - Low-noise, low-dropout (LN-LDO) regulators are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low 1/f noise LDO regulator utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) with an asymmetrical input pair is designed as a second stage. With chopping frequencies up to 1MHz, an output noise spectral density of 32nV/√Hz and PSR of 38dB is achieved at 100kHz. Compared to an equivalent noise density static regulator, the error amplifier silicon area is reduced by 75%. With the current-mode feedback second stage buffer, settling time is reduced by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6μsec settling time for a 50mA load step. The LN-LDO is designed and fabricated on a 0.25μm CMOS process with five layers of metal, occupying 0.88mm2.
AB - Low-noise, low-dropout (LN-LDO) regulators are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low 1/f noise LDO regulator utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) with an asymmetrical input pair is designed as a second stage. With chopping frequencies up to 1MHz, an output noise spectral density of 32nV/√Hz and PSR of 38dB is achieved at 100kHz. Compared to an equivalent noise density static regulator, the error amplifier silicon area is reduced by 75%. With the current-mode feedback second stage buffer, settling time is reduced by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6μsec settling time for a 50mA load step. The LN-LDO is designed and fabricated on a 0.25μm CMOS process with five layers of metal, occupying 0.88mm2.
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U2 - 10.1109/CICC.2006.320913
DO - 10.1109/CICC.2006.320913
M3 - Conference contribution
AN - SCOPUS:39049158731
SN - 1424400767
SN - 9781424400768
T3 - Proceedings of the Custom Integrated Circuits Conference
SP - 213
EP - 216
BT - Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
T2 - IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Y2 - 10 September 2006 through 13 September 2006
ER -