This work presents a linearity enhancement technique for envelope tracked linear power amplifiers (ET-PAs). To enhance linearity, the proposed technique dynamically biases the cascode device with respect to the RF input signal's envelope in a cascoded ET -PA architecture. The effect of supply voltage (VDD) variation on the PA's drain impedance due to the envelope tracking operation is characterized in this work. Furthermore, the impact of variable supply on the AM-PM and IMD3 linearity is analyzed. A class-AB PA using the presented technique is designed and simulated in a CMOS TSMC 65nm process with 2.2V nominal supply voltage. The designed PA demonstrates a saturated output power (Psat) of+19.2dBm with a power gain (Gp) of 16dB for a frequency range of 2.4-2.6GHz, while maintaining maximum power-added efficiency (PAE) of 55%. The supply of this PA is modulated to analyze the effects of envelope tracking on PA performance. With the presented technique, the PA's AM-PM variation is within 1°, IMD3 improves by 4dB, and the PA's drain impedance variation reduces by 37.5% when compared to the ET-PA without the dynamic bias for linearity enhancement.