A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage

Hafijur Rahman; Chaitali Chakrabarti

A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage mechanism of such circuits is the gate leakage. This paper first describes a fast leakage estimation technique based on biasing states for both gate leakage and sub-threshold leakage. Next, it describes a leakage reduction method based on the selective insertion of control points. Simulations on a set of examples show that this method results in the average leakage being 28.7% of the leakage of the baseline circuit whose inputs have already been subjected to the minimum leakage vector (MLV).

Original language	English (US)
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
State	Published - 2004
Event	2004 IEEE International Symposium on Circuits and Systems - Proceedings - Vancouver, BC, Canada Duration: May 23 2004 → May 26 2004

Other

Other	2004 IEEE International Symposium on Circuits and Systems - Proceedings
Country/Territory	Canada
City	Vancouver, BC
Period	5/23/04 → 5/26/04

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage",

abstract = "Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage mechanism of such circuits is the gate leakage. This paper first describes a fast leakage estimation technique based on biasing states for both gate leakage and sub-threshold leakage. Next, it describes a leakage reduction method based on the selective insertion of control points. Simulations on a set of examples show that this method results in the average leakage being 28.7% of the leakage of the baseline circuit whose inputs have already been subjected to the minimum leakage vector (MLV).",

author = "Hafijur Rahman and Chaitali Chakrabarti",

year = "2004",

language = "English (US)",

volume = "2",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

note = "2004 IEEE International Symposium on Circuits and Systems - Proceedings ; Conference date: 23-05-2004 Through 26-05-2004",

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T1 - A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage

AU - Rahman, Hafijur

AU - Chakrabarti, Chaitali

PY - 2004

Y1 - 2004

N2 - Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage mechanism of such circuits is the gate leakage. This paper first describes a fast leakage estimation technique based on biasing states for both gate leakage and sub-threshold leakage. Next, it describes a leakage reduction method based on the selective insertion of control points. Simulations on a set of examples show that this method results in the average leakage being 28.7% of the leakage of the baseline circuit whose inputs have already been subjected to the minimum leakage vector (MLV).

AB - Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage mechanism of such circuits is the gate leakage. This paper first describes a fast leakage estimation technique based on biasing states for both gate leakage and sub-threshold leakage. Next, it describes a leakage reduction method based on the selective insertion of control points. Simulations on a set of examples show that this method results in the average leakage being 28.7% of the leakage of the baseline circuit whose inputs have already been subjected to the minimum leakage vector (MLV).

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UR - http://www.scopus.com/inward/citedby.url?scp=4344565875&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:4344565875

VL - 2

BT - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2004 IEEE International Symposium on Circuits and Systems - Proceedings

Y2 - 23 May 2004 through 26 May 2004

ER -

A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage

Abstract

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ASJC Scopus subject areas

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