A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage

Hafijur Rahman, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Scopus citations

Abstract

Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage mechanism of such circuits is the gate leakage. This paper first describes a fast leakage estimation technique based on biasing states for both gate leakage and sub-threshold leakage. Next, it describes a leakage reduction method based on the selective insertion of control points. Simulations on a set of examples show that this method results in the average leakage being 28.7% of the leakage of the baseline circuit whose inputs have already been subjected to the minimum leakage vector (MLV).

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Volume2
StatePublished - 2004
Event2004 IEEE International Symposium on Circuits and Systems - Proceedings - Vancouver, BC, Canada
Duration: May 23 2004May 26 2004

Other

Other2004 IEEE International Symposium on Circuits and Systems - Proceedings
CountryCanada
CityVancouver, BC
Period5/23/045/26/04

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Rahman, H., & Chakrabarti, C. (2004). A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 2)