Abstract
Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage mechanism of such circuits is the gate leakage. This paper first describes a fast leakage estimation technique based on biasing states for both gate leakage and sub-threshold leakage. Next, it describes a leakage reduction method based on the selective insertion of control points. Simulations on a set of examples show that this method results in the average leakage being 28.7% of the leakage of the baseline circuit whose inputs have already been subjected to the minimum leakage vector (MLV).
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 2 |
| State | Published - 2004 |
| Event | 2004 IEEE International Symposium on Circuits and Systems - Proceedings - Vancouver, BC, Canada Duration: May 23 2004 → May 26 2004 |
Other
| Other | 2004 IEEE International Symposium on Circuits and Systems - Proceedings |
|---|---|
| Country | Canada |
| City | Vancouver, BC |
| Period | 5/23/04 → 5/26/04 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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Rahman, H., & Chakrabarti, C. (2004). A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 2)